Low temperature spacer for advanced semiconductor devices

Patent metadata

Field	Value
Publication number	US-9293557-B2
Application number	US-201414330086-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Feb 20, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor body;
a gate stack disposed atop the semiconductor body; and
a boron nitride spacer in direct contact with sidewalls of the gate stack and at least a portion of the semiconductor body, wherein the boron nitride spacer has a thickness greater than or equal to 1 nm and less than or equal to 20 nm and has a hexagonal bonding configuration.

2. The semiconductor device of claim 1 , wherein the boron nitride spacer has a hexagonal textured structure, and the boron nitride spacer either includes an amorphous region which is less than or equal to 5 nm thick or includes no amorphous region.

3. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises stoichiometric boron nitride.

4. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises boron nitride that has an oxygen content less than or equal to five atomic percent, and boron nitride that, after performing reactive ion etching, has a dielectric constant greater than or equal to 3 and less than or equal to 4.5.

5. The semiconductor device of claim 1 , wherein the semiconductor body comprises at least one of the following: silicon germanium (SiGe), germanium (Ge), and a III-V compound.

6. The semiconductor device of claim 1 , wherein the semiconductor body comprises a silicon layer, atop a silicon-on-insulator (SOI) layer having a buried oxide (BOX) layer, atop a silicon substrate, or the semiconductor body comprises an indium gallium arsenide (InGaAs) layer, atop an indium aluminum arsenide (InAlAs) layer, atop an indium phosphide (InP) substrate.

7. The semiconductor device of claim 1 , wherein boron nitride spacer has a wet etch rate that is less than a wet etch rate of silicon nitride (Si 3 N 4 ) for one or more etchants.

8. The semiconductor device of claim 1 , wherein the semiconductor device is a planar FET or a FinFET.

9. The semiconductor device of claim 1 , wherein the boron nitride spacer comprises boron nitride deposited on the sidewalls of the gate stack and the at least a portion of the semiconductor body using one or both of atomic layer deposition (ALD) and plasma enhanced atomic layer deposition (PEALD).

10. A semiconductor device comprising:
a semiconductor body;
a gate stack disposed atop the semiconductor body;
a liner layer in direct contact with sidewalls of the gate stack and at least a portion of the semiconductor body; and
a boron nitride spacer in direct contact with at least a portion of the liner layer, wherein the boron nitride spacer has a thickness greater than or equal to 1 nm and less than or equal to 20 nm and has a hexagonal bonding configuration.

11. The semiconductor device of claim 10 , wherein the boron nitride spacer has a hexagonal textured structure, and the boron nitride spacer either includes an amorphous region which is less than or equal to 5 nm thick or includes no amorphous region.

12. The semiconductor device of claim 10 , wherein the boron nitride spacer comprises stoichiometric boron nitride.

13. The semiconductor device of claim 10 , wherein the boron nitride spacer comprises boron nitride that has an oxygen content less than or equal to five atomic percent, and boron nitride that, after performing reactive ion etching, has a dielectric constant greater than or equal to 3 and less than or equal to 4.5.

14. The semiconductor device of claim 10 , wherein the semiconductor body comprises at least one of the following: silicon germanium (SiGe), germanium (Ge), and a III-V compound.

15. The semiconductor device of claim 10 , wherein the semiconductor body comprises a silicon layer, atop a silicon-on-insulator (SOI) layer having a buried oxide (BOX) layer, atop a silicon substrate, or the semiconductor body comprises an indium gallium arsenide (InGaAs) layer, atop an indium aluminum arsenide (InAlAs) layer, atop an indium phosphide (InP) substrate.

16. The semiconductor device of claim 10 , wherein boron nitride spacer has a wet etch rate that is less than a wet etch rate of silicon nitride (Si 3 N 4 ) for one or more etchants.

17. The semiconductor device of claim 10 , wherein the semiconductor device is a planar FET or a FinFET.

18. The semiconductor device of claim 10 , wherein the liner layer comprises at least one of the following: silicon nitride and a silicon oxide.

19. The semiconductor device of claim 10 , wherein the boron nitride spacer comprises boron nitride deposited on the least a portion of the liner layer using one or both of atomic layer deposition (ALD) and plasma enhanced atomic layer deposition (PEALD).

Assignees

• IBM

Inventors

• Chan Kevin K
• Grill Alfred
• Neumayer Deborah A
• Park Dae-Gyu
• Sosa Norma E
• Yang Min

Classifications

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/671 Primary

  the conductor having lateral variation in doping or structure · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title