Semiconductor light detecting element having silicon substrate and conductor

US9293499B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9293499-B2
Application numberUS-201113634249-A
CountryUS
Kind codeB2
Filing dateFeb 22, 2011
Priority dateApr 14, 2010
Publication dateMar 22, 2016
Grant dateMar 22, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor light detecting element is provided with a silicon substrate having a semiconductor layer, and an epitaxial semiconductor layer grown on the semiconductor layer and having a lower impurity concentration than the semiconductor layer; and conductors provided on a surface of the epitaxial semiconductor layer. A photosensitive region is formed in the epitaxial semiconductor layer. Irregular asperity is formed at least in a surface opposed to the photosensitive region in the semiconductor layer. The irregular asperity is optically exposed.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor light detecting element comprising: a silicon substrate having a semiconductor layer having a first impurity concentration, and an epitaxial semiconductor layer grown on the semiconductor layer and having a second impurity concentration lower than the first impurity concentration; and a conductor provided on a surface of the epitaxial semiconductor layer, wherein a photosensitive region is formed in the epitaxial semiconductor layer, wherein irregular asperity is formed at least in a surface opposed to the photosensitive region in the semiconductor layer, wherein the irregular asperity is optically exposed, wherein the irregular asperity is formed by applying pulsed laser light, light incident into the silicon substrate is scattered, diffused, or reflected by the irregular asperity to travel in the silicon substrate, and the photosensitive region is configured to generate an electric charge in response to incident light. 2. The semiconductor light detecting element according to claim 1 , wherein the conductor comprises a photogate electrode provided on the surface of the epitaxial semiconductor layer, and first and second gate electrodes provided adjacent to the photogate electrode on the surface of the epitaxial semiconductor layer, the semiconductor light detecting element further comprising: first and second semiconductor regions formed in the epitaxial semiconductor layer, for reading out respective charges flowing from a region immediately below the photogate electrode to immediately below the first and second gate electrodes, wherein the irregular asperity is formed at least in a surface opposed to the region immediately below the photogate electrode in the semiconductor layer. 3. The semiconductor light detecting element according to claim 1 , wherein a photodiode to generate charge in a quantity according to an intensity of incident light is formed as the photosensitive region in the epitaxial semiconductor layer, and wherein the irregular asperity is formed at least in a surface opposed to the photodiode in the semiconductor layer. 4. The semiconductor light detecting element according to claim 3 , further comprising: an amplification transistor to output a voltage value according to a quantity of charge input at a gate terminal thereof; a transfer transistor to transfer the charge generated in the photodiode, to the gate terminal of the amplification transistor; a discharge transistor to discharge the charge at the gate terminal of the amplification transistor; and a selection transistor to selectively output the voltage value output from the amplification transistor. 5. The semiconductor light detecting element according to claim 1 , wherein the epitaxial semiconductor layer has a plurality of multiplication regions forming pn junctions at interfaces to the semiconductor layer and configured to achieve avalanche multiplication of carriers generated with incidence of light to be detected, wherein the conductor includes a plurality of resistors each having two end portions, provided for the respective multiplication regions, electrically connected to the epitaxial semiconductor layer through one of the end portions, and connected to a signal conductor line through the other of the end portions, and wherein the irregular asperity is formed at least in a surface opposed to each of the multiplication regions in the semiconductor layer. 6. The semiconductor light detecting element according to claim 1 , wherein the epitaxial semiconductor layer has a plurality of multiplication regions to achieve avalanche multiplication of carriers generated with incidence of light, wherein semiconductor regions forming pn junctions at interfaces to the epitaxial semiconductor layer are formed corresponding to the multiplication regions in the epitaxial semiconductor layer, wherein the conductor includes a plurality of resistors each having two end portions, provided for the respective semiconductor regions in the epitaxial semiconductor layer, electrically connected to the respective semiconductor regions in the epitaxial semiconductor layer through one of the end portions, and connected to a signal conductor line through the other of the end portions, and wherein the irregular asperity is formed at least in a surface opposed to each of the semiconductor regions in the semiconductor layer.

Assignees

Inventors

Classifications

  • Surface textures, e.g. pyramid structures · CPC title

  • Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

  • H10F39/199Primary

    Back-illuminated image sensors · CPC title

  • H10F39/807Primary

    Pixel isolation structures · CPC title

  • Electricity · mapped topic

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What does patent US9293499B2 cover?
A semiconductor light detecting element is provided with a silicon substrate having a semiconductor layer, and an epitaxial semiconductor layer grown on the semiconductor layer and having a lower impurity concentration than the semiconductor layer; and conductors provided on a surface of the epitaxial semiconductor layer. A photosensitive region is formed in the epitaxial semiconductor layer. I…
Who is the assignee on this patent?
Mase Mitsuhito, Sakamoto Akira, Suzuki Takashi, and 3 more
What technology area does this patent fall under?
Primary CPC classification H10F39/199. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).