Flexible display device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9293485-B2
Application number	US-201514744586-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	May 28, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate.

First claim

What is claimed is:

1. A method for manufacturing a flexible display device comprising:
forming a substrate defined by a display area and a non-display area being an outer region of the display area and including a link area and a pad area, using a flexible material;
forming a buffer film over the surface of the substrate;
forming a gate insulation film over the surface of the buffer film;
forming gate lines in the display area on the gate insulation film;
forming an interlayer insulation film over the entire surface of the gate insulation film such that the interlayer insulation film covers the gate lines;
forming a first bending hole passing through at least the gate insulation film and the interlayer insulation film in a bending area, wherein the bending area bends such that the pad area of the non-display area is disposed on the lower surface of the substrate;
forming data lines and a plurality of links, wherein the data lines are formed in the display area on the interlayer insulation film such that the data lines cross the gate lines, and wherein the plurality of links are connected to signal lines selected from the gate lines and the data lines in the linking area on the interlayer insulation film;
forming a protective film over the surface of the interlayer insulation film such that the protective film covers the data lines and the links;
forming a plurality of pads connected to the links and connected to an exterior circuit to supply a driving signal to the signal line on the protective film; and
bending the bending area such that the pads are disposed on the back side of the surface of the substrate.

2. The method according to claim 1 , further comprising: forming an anti-etching layer in at least a part including the bending area of the non-display area on the substrate, before formation of the buffer film,
wherein the first bending hole further passes through the buffer film to expose at least a part of the anti-etching layer, during formation of the first bending hole, and
the link directly contacts at least a part of the anti-etching layer exposed through the first bending hole in the bending area, during formation of the link.

3. The method according to claim 2 , further comprising forming at least one second bending hole passing through the protective film and the anti-etching layer in the periphery of the link in the first bending hole to expose a part of the substrate, after formation of the protective film.

4. The method according to claim 2 , wherein the anti-etching layer is further formed in the pad area during formation of the anti-etching layer, and
the first bending hole is further formed in the pad area during formation of the first bending hole.

5. The method according to claim 2 , wherein, during formation of the anti-etching layer, the anti-etching layer is formed using a material having softness higher than the insulation films and having an etch ratio lower than the insulation films upon etching to form the first bending hole.

6. The method according to claim 2 , wherein, during formation of the anti-etching layer, the anti-etching layer is formed using at least one of ITO, Mo, Ti, Cu, Ag, Au and a-Si.

7. The method according to claim 2 , wherein the anti-etching layer includes a plurality of anti-etching patterns corresponding to the links, during formation of the anti-etching layer, and
the first bending hole includes a plurality of first bending holes to expose at least a part of the respective anti-etching patterns during formation of the first bending hole, and
the links contact the anti-etching patterns exposed through the first bending holes, respectively, during formation of the data lines and the links.

8. The method according to claim 1 , further comprising:
forming an anti-etching layer in the bending area of the non-display area on the substrate, before formation of the buffer film; and
forming a pre-bending hole passing through the buffer film in the bending area such that the pre-bending hole exposes at least a part of the anti-etching layer, after formation of the buffer film.
wherein the first bending hole passes through the gate insulation film and the interlayer insulation film in the pre-bending hole, in a width smaller than the pre-bending hole to expose the anti-etching layer, during formation of the first bending hole, and
the link directly contacts at least a part of the anti-etching layer exposed through the pre-bending hole and the first bending hole in the bending area, during formation of the link.

Assignees

• Lg Display Co Ltd

Inventors

• Youn Sang-Cheon
• Jin Hyoung-Suk
• Kang Chang-Heon
• Kwon Se-Yeoul

Classifications

• H10W72/90 Primary

  Bond pads, in general · CPC title

• Y02E10/549

  Organic PV cells · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title