Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Semiconductor device and method of manufacturing the same
US9293441B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9293441-B2 |
| Application number | US-201113252714-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2011 |
| Priority date | Dec 9, 2005 |
| Publication date | Mar 22, 2016 |
| Grant date | Mar 22, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
First claim
Opening claim text (preview).
The invention claimed is: 1. A wireless communications device, comprising: a flash memory comprising: a plurality of stacked semiconductor chips, at least one of the semiconductor chips comprising: a semiconductor substrate; a first insulating layer on a top face and side faces of the semiconductor substrate with concavities on side faces thereof, wherein said concavities have planar side surfaces that extend vertically from a first edge at the top face of the semiconductor su…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9293441B2 cover?
- The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; an…
- Who is the assignee on this patent?
- Hoshino Masataka, Kasai Junichi, Meguro Kouichi, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).