Semiconductor package and semiconductor device

Patent metadata

Field	Value
Publication number	US-9293419-B2
Application number	US-201514680039-A
Country	US
Kind code	B2
Filing date	Apr 6, 2015
Priority date	Apr 17, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A semiconductor package includes a first substrate including a first surface layer where a first pad region and a second pad region are formed, the first pad region including a plurality of first pads for connection to a first IC, the second pad region including a plurality of second pads for connection to a second substrate, and a second surface layer where a third pad region including a plurality of third pads for connection to a second IC is formed, the second surface layer being formed on an opposite side of the first surface layer. The second pads surround the first pad region in at least three rows, and one or more pads included in the second pads and arranged in an inner portion are connected to one or more pads included in the first pads and to one or more pads included in the third pads.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first substrate including
a first surface layer where a first pad region and a second pad region are formed, the first pad region including a plurality of first pads for connection to a first integrated circuit (IC), the second pad region including a plurality of second pads for connection to a second substrate, and
a second surface layer where a third pad region including a plurality of third pads for connection to a second IC is formed, the second surface layer being formed on an opposite side of the first surface layer, wherein

the plurality of second pads surround the first pad region in at least three rows, and
one or more pads included in the plurality of second pads and arranged in an inner portion of the second pad region are connected to one or more pads included in the plurality of first pads and to one or more pads included in the plurality of third pads.

2. The semiconductor package according to claim 1 , wherein
one or more pads included in the plurality of second pads and arranged in an outer portion are connected to one or more pads included in the plurality of first pads.

3. The semiconductor package according to claim 1 , wherein
one or more pads included in the plurality of second pads and arranged in a middle portion are connected to one or more pads included in the plurality of third pads.

4. A semiconductor device comprising:
a semiconductor package;
a first integrated circuit (IC) mounted in a first pad region;
a second IC mounted in a third pad region;
a second substrate; and
one or more conductive members that connect one or more pads arranged in a middle portion and an outer portion of a second pad region and the second substrate, wherein
the semiconductor package includes
a first substrate including
a first surface layer where the first pad region and the second pad region are formed, the first pad region including a plurality of first pads for connection to the first IC, the second pad region including a plurality of second pads for connection to the second substrate, and
a second surface layer where the third pad region including a plurality of third pads for connection to the second IC is formed, the second surface layer being formed on an opposite side of the first surface layer, wherein

the plurality of second pads surround the first pad region in at least three rows, and
one or more pads included in the plurality of second pads and arranged in an inner portion of the second pad region are connected to one or more pads included in the plurality of first pads and to one or more pads included in the plurality of third pads.

5. The semiconductor device according to claim 4 , further comprising:
a third substrate arranged between the second pad region and the second substrate, wherein
the one or more conductive members include
one or more first conductive members that connect one or more pads arranged in the middle portion and the outer portion of the second pad region and the third substrate, and
one or more second conductive members that connect the third substrate and the second substrate.

6. A semiconductor device comprising:
a semiconductor package;
a second integrated circuit (IC) mounted in a third pad region;
a second substrate; and
one or more conductive members that connect one or more pads arranged in an inner portion and a middle portion of a second pad region and the second substrate, wherein
the semiconductor package includes
a first substrate including
a first surface layer where a first pad region and the second pad region are formed, the first pad region including a plurality of first pads for connection to a first IC, the second pad region including a plurality of second pads for connection to the second substrate, and

a second surface layer where the third pad region including a plurality of third pads for connection to the second IC is formed, the second surface layer being formed on an opposite side of the first surface layer, wherein
the plurality of second pads surround the first pad region in at least three rows, and
one or more pads included in the plurality of second pads and arranged in the inner portion of the second pad region are connected to one or more pads included in the plurality of first pads and to one or more pads included in the plurality of third pads.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Nakamura Maki
• Fujita Suguru

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title