Package with terminal pins with lateral reversal point and laterally exposed free end

Patent metadata

Field	Value
Publication number	US-9293400-B2
Application number	US-201514590021-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Jan 7, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A package ( 120 ), wherein the package ( 120 ) has at least one electronic chip ( 124 ), an encapsulation body ( 138 ) that encapsulates the electronic chip(s) ( 124 ), and a plurality of terminal pins ( 122 ) to connect the electronic chip(s) ( 124 ), wherein each of the said terminal pins ( 122 ) has an encapsulated section ( 126 ), which is encapsulated at least partially by the encapsulation body ( 138 ) and has an exposed section ( 128 ) that protrudes from the encapsulation body ( 138 ), and wherein at least a portion of the exposed sections ( 128 ) laterally extends from the encapsulation body ( 138 ) up to a reversal point ( 130 ) and laterally extends back from the reversal point ( 130 ) to the encapsulation body ( 138 ), so that a free end ( 132 ) of the exposed sections ( 128 ) is laterally aligned with or to a corresponding side wall ( 134 ) of the encapsulation body ( 138 ) or is spaced from the corresponding side wall ( 134 ) of the encapsulation body ( 138 ) laterally outwardly.

First claim

The invention claimed is:

1. A package, wherein the package comprises:
at least one electronic chip;
an encapsulation body that at least partially encapsulates the at least one electronic chip;
a plurality of terminal pins to connect the at least one electronic chip, wherein each of the said terminal pins comprises an encapsulated section that is encapsulated by the encapsulation body, and an exposed section that protrudes from the encapsulation body;
wherein at least a part of the exposed sections extends laterally from the encapsulation body up to a reversal point and extends back laterally from the reversal point towards the encapsulation body, so that a free end of the exposed sections is laterally aligned with a corresponding side wall of the encapsulation body, or is spaced from the corresponding side wall of the encapsulation body laterally outwardly;
wherein the exposed sections are continuously curved, in particular kinkfree.

2. The package according to claim 1 , wherein the terminal pins are configured such that the free end of the exposed sections is spaced vertically with respect to an adjacent main surface of the encapsulation body.

3. The package according to claim 1 , wherein an entire outer surface of the exposed sections, which is turned away from the encapsulation body is convex.

4. The package according to claim 1 , wherein the terminal pins are configured such that a vertical distance between the section of the exposed sections extending from the encapsulation body and the remaining section that extends from the reversal point that laterally extends back to the encapsulation body is reduced by exerting a compressive force when mounting the package on a peripheral electronic device.

5. The package according to claim 1 , wherein a portion of the exposed sections, which laterally extends up to the reversal point, with respect to an axis of symmetry is axially symmetric with respect to a different portion of the exposed sections, which laterally extends from the reversal point back into the direction of the encapsulation body, wherein the axis of symmetry is in a plane, which is parallel to opposite main surfaces of the encapsulation body.

6. The package according to claim 1 , wherein at least a portion of the exposed sections is substantially C-shaped.

7. The package according to claim 1 , wherein at least a part of the exposed sections extends from the lateral side wall of the encapsulation body.

8. The package according to claim 1 , wherein the exposed sections of the terminal pins extend from all four lateral sides of the encapsulation body beyond the encapsulation body.

9. The package according to claim 1 , wherein a ratio between a lateral extension of the package and a thickness of the package is greater than five, in particular, greater than nine.

10. The package according to claim 1 , wherein the package is configured as a flat package, and in particular, as a quad flat package.

11. The package according to claim 1 , wherein a thickness of the package is less than 1.7 mm.

12. The package according to claim 1 , wherein the terminal pins have a shape selected from a group consisting of a bent wire and a bent tape.

13. The package according to claim 1 wherein the at least one electronic chip is mounted on a chip carrier, in particular, a lead frame.

14. The package according to claim 1 , wherein the at least one electronic chip is electrically connected to the terminal pins using bonding wires.

15. The package according to claim 1 , wherein the plurality of terminal pins are formed to connect the at least one electronic chip to a peripheral electronic device.

16. The package according to claim 1 , wherein the respective free end of the exposed sections is closer to a peripheral electronic device, to which the package is to be connected, than the remainder of the respective exposed section between the respective free end and the respective reversal point.

17. The package according to claim 1 , wherein the free ends of the exposed sections are directed inwardly, in particular, facing one another.

18. An electronic assembly, wherein the electronic assembly comprises:
a peripheral electronic device, comprising a plurality of electrical contacts; and
a package according to claim 1 ;
wherein at least a part of the terminal pins of the package is electrically connected to a respective one of the electrical contacts of the peripheral electronic device.

19. The arrangement according to claim 18 , wherein areas of the exposed sections that are turned away from the encapsulation body are soldered to the electrical contacts.

20. The arrangement according to claim 18 , wherein the peripheral electronic device is configured as a printed circuit board.

21. The arrangement according to claim 18 , wherein a material of the encapsulation body has a larger coefficient of thermal expansion than a material of the peripheral electronic device.

22. Method for producing a package, wherein the method comprises:
connecting a plurality of terminal pins to at least one electronic chip;
at least partial encapsulating of the at least one electronic chip and partial encapsulating of the terminal pins by an encapsulation body such that each of the terminal pins comprises an encapsulated section that is encapsulated by the encapsulation body, and an exposed section extending beyond the encapsulation body;
configuring at least a part of the exposed sections such that these extend laterally from the encapsulation body up to a reversal point and from the reversal point laterally back to the encapsulation body, so that a free end of the exposed sections is laterally aligned with an associated side wall of the encapsulation body, or is laterally outwardly spaced from an associated side wall of the encapsulation body;
wherein the exposed sections are continuously curved, in particular kinkfree.

23. Method according to claim 22 , wherein the plurality of terminal pins are formed for electrically contacting the at least one electronic chip to a peripheral electronic device.

Assignees

• Infineon Technologies Ag

Inventors

• Ananiev Sergey

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title