Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9293347-B2
Application number	US-201214381562-A
Country	US
Kind code	B2
Filing date	May 18, 2012
Priority date	May 18, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP 1 formed on the substrate. The upper surface of the semiconductor layer EP 1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP 1.

First claim

What is claimed is:

1. A semiconductor device comprising:
a MISFET including
an SOI substrate having a support substrate, an insulating layer on the support substrate, and a semiconductor layer on the insulating layer;
a gate electrode formed on the semiconductor layer, via a gate insulating film; and
a first epitaxial layer formed on the semiconductor layer,

wherein a first insulating film is formed on the semiconductor layer so as to cover the first epitaxial layer,
wherein the gate electrode is buried in a first trench formed in the first insulating film,
wherein the first epitaxial layer has an upper surface positioned higher than an upper surface of the semiconductor layer directly below the gate electrode,
wherein an end part of the gate electrode is positioned on the first epitaxial layer in a gate length direction of the MISFET,
wherein a source or drain semiconductor region is formed in the first epitaxial layer and the semiconductor layer,
wherein the source or drain semiconductor region has a first region and a second region adjacent to the first region and has an impurity concentration higher than an impurity concentration of the first region, and
wherein at least part of the first region is positioned directly below the gate electrode.

2. The semiconductor device according to claim 1 ,
wherein the first epitaxial layer has a tilted. side surface in a gate length direction of the MISFET, and
wherein the end part of the gate electrode is positioned on the tilted side surface of the first epitaxial layer in the gate length direction of the MISFET.

3. The semiconductor device according to claim 2 ,
wherein the gate insulating film. is formed on a side surface and a bottom surface of the first trench, and
the gate electrode is buried in the first trench via the gate insulating film.

4. A method of manufacturing a semiconductor device having a. MISFET, the method comprising the steps of:
(a) preparing an SOI substrate having a support substrate, an insulating layer on the support substrate, and a semiconductor layer on the insulating layer;
(b) forming a dummy gate on the semiconductor layer;
c) after the step (b), forming a first epitaxial layer on the semiconductor layer, such that an upper surface of the first epitaxial layer is higher than a upper surface of the semiconductor layer formed below the dummy gate;
(d) after the step (c), forming a first sidewall film on a sidewall of the dummy gate such that the first sidewall flim is formed on the first epitaxial layer;
(e) after the step (d), forming a first insulating film on the semiconductor layer so as to cover the dummy gate;
(f) after the step (e), removing part. of the first insulating film to expose an upper surface of the dummy gate;
(g) after the step (f), removing the dummy gate and the first sidewall film to form a first trench; and
(h) after the step (g), forming a gate electrode in the first trench via a gate insulating film,
wherein, after the step (c), a first semiconductor region is formed in the first epitaxial layer and the semiconductor layer by a step of ion implantation with the dummy gate as a mask,
wherein, after the step (d), a second semiconductor region having higher impurity concentration than the first semiconductor region id formed in the first epitaxial layer and the semiconductor layer by a step of ion implantation with the dummy gate and the first sidewall film as a mask, and
wherein, after the step(h), an end part of the gate electrode is positioned on the first epitaxial layer and on the first semiconductor region in a gate length direction of the MISFET.

5. The method of manufacturing the semiconductor device according to claim 4 ,
wherein the dummy gate formed in the step (d) includes a polysilicon film,
after the step (b) and before the step (c), the method comprises
(b 1 ) a step of forming a second sidewall film on the sidewall of the dummy gate,
wherein, in the step (d), the first sidewall film is formed. on the sidewall of the dummy gate via the second sidewall film, and
wherein, in the step (g), the dummy gate, the first sidewall film, and the second sidewall film are removed to form the first trench.

6. The method of manufacturing the semiconductor device according to claim 5 ,
wherein the dummy gate is formed of a second insulating film, the polysilicon film on the second insulating film, and a third insulating film on the polysilicon film.

7. The method of manufacturing the semiconductor device according to claim 6 ,
wherein the first insulating film. has a silicon nitride film and a fourth insulating film on the silicon nitride film, and
the first sidewall film and the second sidewall film are made of silicon oxide.

8. The method of manufacturing the semiconductor device according to claim 5 ,
wherein the first insulating film has a silicon nitride. film and a fourth insulating film on the silicon nitride film, and
wherein the first sidewall film and the second sidewall film are made of silicon nitride.

9. The method of manufacturing the semiconductor device according to claim 4 ,
wherein, in the step (c), the first epitaxial layer is formed so that the first epitaxial layer has a tilted side surface,
wherein in the step (d), the first sidewall film is formed on the tilted side surface of the first epitaxial layer, and
wherein the end part of the gate electrode formed in the step (h) is positioned on the tilted side surface of the first epitaxial layer.

10. The method of manufacturing the semiconductor device according to claim 4 ,
wherein, after the step (d) and before the step (e), the method comprises the steps of
(d 2 ) forming a third sidewall film on the sidewall of the dummy gate via the first sidewall film, and
(d 3 ) after the step (d 2 ), forming a metal suicide layer on the first epitaxial layer, and

wherein in the step (g), the first sidewall film is removed, and the third sidewall film is left.

11. The method of manufacturing the semiconductor device according to claim 4 ,
wherein, after the step (d) and before the step (e), the method comprises
(d 4 ) a step of forming a second epitaxial layer for source/drain formation on the first epitaxial layer.

12. The method. of manufacturing the semiconductor device according to claim 4 ,
wherein. the first sidewall film is formed of a laminated layer of a fourth sidewall film and a fifth sidewall film,
wherein the fourth. sidewall film is on a side closer to the dummy gate than the fifth sidewall film, and
wherein, in the step (g), the fourth sidewall film is removed, and the fifth sidewall film. is left.

Assignees

• Yamamoto Yoshiki
• Makiyama Hideki
• Tsunomura Takaaki
• Iwamatsu Toshiaki
• Renesas Electronics Corp

Inventors

• Yamamoto Yoshiki
• Makiyama Hideki
• Tsunomura Takaaki
• Iwamatsu Toshiaki

Classifications

• H10P14/61 Primary

  using masks · CPC title

• H10D30/635 Primary

  having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title