Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9293335-B2
Application number	US-201313912441-A
Country	US
Kind code	B2
Filing date	Jun 7, 2013
Priority date	Jan 9, 2009
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
conductive layers and insulating layers repeatedly and alternatingly stacked on a substrate;
an active portion penetrating the conductive layers and the insulating layers to connect the substrate; and
a blocking insulating layer, a charge storage layer, and a charge tunneling layer sequentially disposed from the conductive layers to the active portion;
wherein the conductive layers are electron injecting layers that inject electrons from the active portion to the charge storage layer through the charge tunneling layer;
wherein the charge tunneling layer includes a first tunnel insulating layer, a second tunnel insulating layer, and a third tunnel insulating layer sequentially disposed from the charge storage layer to the active portion, wherein the first, second, and third tunnel insulating layers are charge tunneling layers;
wherein the second tunnel insulating layer includes a silicon-nitride-oxide layer; and
wherein the second tunnel insulating layer has a higher dielectric constant than the first tunnel insulating layer and the third tunnel insulating layer.

2. The semiconductor device as claimed in claim 1 , wherein the first tunnel insulating layer includes at least one of an oxide or a nitride-oxide.

3. The semiconductor device as claimed in claim 1 , wherein the first tunnel insulating layer has a different oxygen concentration or different nitrogen concentration from the second tunnel insulating layer.

4. The semiconductor device as claimed in claim 1 , wherein the charge storage layer comprises a silicon nitride layer.

5. The semiconductor device as claimed in claim 1 , wherein the first tunnel insulating layer, the second tunnel insulating layer, and the third tunnel insulating layer have different oxygen concentration gradients or nitrogen concentration gradients from one another.

6. The semiconductor device as claimed in claim 1 , wherein the active portion is in direct contact with the substrate.

7. The semiconductor device as claimed in claim 1 , further comprising an opening penetrating the conductive layers and the insulating layers, such that at least a portion of the substrate is exposed,
wherein at least one of the blocking insulating layer, the charge storage layer, and the charge tunneling layer is disposed in the opening.

8. The semiconductor device as claimed in claim 1 , wherein the conductive layers comprise a lower selective gate, control gates, and an upper selective gate sequentially disposed on the substrate.

9. The semiconductor device as claimed in claim 1 , wherein the first tunnel insulating layer and the third tunnel insulating layer are each a silicon oxide layer.

10. A semiconductor device, comprising:
an active portion;
a gate insulating layer surrounding a side surface of the active portion; and
a control gate surrounding a side surface of the gate insulating layer,
wherein the gate insulating layer includes a blocking insulating layer, a charge storage layer, and a charge tunneling layer sequentially disposed from the control gate to the active portion,
wherein the charge tunneling layer includes a first tunnel insulating layer, a second tunnel insulating layer, and a third tunnel insulating layer sequentially disposed from the charge storage layer to the active portion, wherein the first, second, and third tunnel insulating layers are charge tunneling layers;
wherein the first tunnel insulating layer, the second tunnel insulating layer, and the third tunnel insulating layer have different oxygen concentration gradients or nitrogen concentration gradients from one another; and
wherein the second tunnel insulating layer has a higher dielectric constant than the first tunnel insulating layer and the third tunnel insulating layer.

11. The semiconductor device as claimed in claim 10 , wherein the control gate is an electron injecting layer that injects electrons from the active portion to the charge storage layer through the charge tunneling layer by Fowler-Nordenheim tunneling.

12. The semiconductor device as claimed in claim 10 , wherein the first tunnel insulating layer, the second tunnel insulating layer, and the third tunnel insulating layer comprise a silicon oxide layer, a silicon-nitride-oxide layer, and a silicon oxide layer respectively.

13. The semiconductor device as claimed in claim 10 , wherein each of the first tunnel insulating layer and the second tunnel insulating layer includes at least one of an oxide or a nitride-oxide.

14. The semiconductor device as claimed in claim 10 , wherein the first tunnel insulating layer has a different oxygen concentration or different nitrogen concentration from the second tunnel insulating layer.

15. The semiconductor device as claimed in claim 1 , wherein the charge storage layer includes polysilicon.

16. The semiconductor device as claimed in claim 10 , wherein the charge storage layer includes polysilicon.

17. The semiconductor device as claimed in claim 1 , wherein a first surface of the first tunnel insulating layer is in direct contact with the charge storage layer, and a second surface opposite to the first surface of the first tunnel insulating layer is in direct contact with the second tunnel insulating layer.

18. A semiconductor device, comprising:
conductive layers and insulating layers repeatedly and alternatingly stacked on a substrate;
an active portion penetrating the conductive layers and the insulating layers to connect the substrate; and
a blocking insulating layer, a charge storage layer, and a charge tunneling layer sequentially disposed from the conductive layers to the active portion;
wherein the charge storage layer includes a silicon nitride layer;
wherein the charge tunneling layer includes a first tunnel insulating layer, a second tunnel insulating layer, and a third tunnel insulating layer sequentially disposed from the charge storage layer to the active portion, wherein the first, second, and third tunnel insulating layers are charge tunneling layers; and
wherein the third tunnel insulating layer is in direct contact with the active portion;
wherein a nitrogen concentration of the second tunnel insulating layer is greater than respective nitrogen concentrations of the first and third tunnel insulating layers
wherein the second tunnel insulating layer has a higher dielectric constant than the first tunnel insulating layer and the third tunnel insulating layer.

19. The semiconductor device as claimed in claim 18 , wherein the conductive layers are electron injecting layers that inject electrons from the active portion to the charge storage layer through the charge tunneling layer.

20. The semiconductor device as claimed in claim 18 , wherein the first tunnel insulating layer is in direct contact with the charge storage layer.

Assignees

• Kim Jingyun
• Lee Myoungbum
• Shin Seungmok
• Samsung Electronics Co Ltd

Inventors

• Kim Jingyun
• Lee Myoungbum
• Shin Seungmok

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title