Multi-level cell memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9293210-B2
Application number	US-201314096281-A
Country	US
Kind code	B2
Filing date	Dec 4, 2013
Priority date	Dec 4, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch.

First claim

What is claimed is:

1. A method of operating a non-volatile memory device, comprising:
performing a first hard decision read operation that includes applying a first read voltage to a selected word line of the non-volatile memory device;
storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device;
performing a second hard decision read operation that includes generating hard decision data by applying a second read voltage to the selected word line, the second read voltage being higher than the first read voltage;
generating a first soft decision value using a result of the first hard decision read operation stored at the first latch without applying a first soft decision read voltage to the selected word line;
storing the first soft decision value at a second latch of the page buffer;
generating a second soft decision value by applying a soft decision read voltage to the selected word line, the soft decision read voltage being higher than the second read voltage; storing the second soft decision value at a third latch of the page buffer; and
generating soft decision data using the page buffer by performing a logical operation on the first soft decision value and the second soft decision value.

2. The method of claim 1 , wherein the first hard decision read operation is a coarse read operation.

3. The method of claim 1 , wherein the second hard decision read operation is a fine read operation.

4. The method of claim 1 , further comprising:
performing an additional error bit correction operation using the soft decision data if an error bit correction operation on the result of the second hard decision read operation fails.

5. The method of claim 1 , wherein the logical operation is an XNOR operation.

6. The method of claim 1 , further comprising:
performing an error correction operation using the hard decision data; and
performing an additional error correction operation using the soft decision data if the error correction operation using the hard decision data fails.

7. The method of claim 1 , wherein
at execution of the applying the soft decision read voltage, selectively pre-charging bit lines connected to memory cells of the non-volatile device based on the result of the second hard decision read operation.

8. The method of claim 1 , further comprising:
performing a third hard decision read operation using a fourth voltage that is higher than the third voltage; and
at execution of the applying the soft decision read voltage, selectively pre-charging bit lines connected to memory cells of the non-volatile memory device that each have a threshold voltage between the second and the fourth voltage if results of the second hard decision read operation and the third hard decision read operation are stored in the page buffer.

9. A method of operating a non-volatile memory device, comprising:
performing a first read operation that includes applying a first voltage to a selected word line of the non-volatile memory device;
storing a result of the first read operation at a first latch of a page buffer of the non-volatile memory device;
performing a second read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage;
performing an error correction operation on a result of the second read operation; and
performing an additional error correction operation using soft decision data if the error correction operation on the result of the second read operation fails,
generating the soft decision data by,
performing a third read operation that includes applying a third voltage to the selected word line, the third voltage being higher than the second voltage,
storing a result of the third read operation in another latch of the page buffer, and
performing a logical operation using the result of the first read operation stored in the first latch and the result of the third read operation stored in the other latch.

10. The method of claim 3 , wherein the logical operation is an XNOR operation.

11. The method of claim 9 , wherein
the first read operation is a coarse read operation, and
the second read operation is a fine read operation.

12. The method of claim 9 , further comprising:
selectively pre-charging bit lines connected to memory cells of the non-volatile memory device, based on the result of the second read operation, at execution of the third read operation.

13. The method of claim 9 , wherein
the non-volatile memory device includes a plurality of a NAND strings arranged in rows and columns,
each NAND strings includes a plurality of memory cells stacked vertically on each other between a ground selection transistor and a string selection transistor,
the non-volatile memory device includes a plurality of bit lines,
each one of the plurality of bit lines is connected to the plurality of NAND strings in a same column,
the selected word line is one of a plurality of word lines in the non-volatile memory device, and
each one of the plurality of word lines is connected to a corresponding one of the plurality of memory cells at a same height in the plurality of NAND strings in a same row.

14. A method of operating a non-volatile memory device, comprising:
performing a first hard decision read operation that includes applying a first voltage to a selected word line of the non-volatile memory device;
storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device;
performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage;
generating a first soft decision value using a result of the first hard decision read operation stored at the first latch;
generating a second soft decision value by performing a soft decision read operation that includes applying a third voltage to the selected word line, the third voltage being higher than the second voltage; and
performing a pre-charge operation based on a result of the second hard decision read operation, the pre-charge operation including being one of:
selectively pre-charging bit lines connected to off-state cells of the non-volatile memory device, based on the result of the second hard decision read operation, at execution of the soft decision read operation, the off-state cells each having a threshold voltage higher than the second voltage, and
performing a third hard decision read operation using a fourth voltage that is higher than the third voltage, and selectively pre-charging bit lines connected to memory cells of the non-volatile memory device having a threshold voltage between the second and the fourth voltage, at execution of the soft decision read operation, if results of the second hard decision read operation and the third hard decision read operations are stored in the page buffer.

15. The method of claim 14 , wherein the pre-charge operation based on the result of the second hard decision read operation is:
selectively pre-charging bit lines connected to off-state cells of the non-volatile memory device, based on the result of the second hard decision read operation, at execution of the soft decision read operation, the off-state cells each have a threshold voltage higher than the second voltage.

16. The method of claim 14 , wherein the pre-charge operation based on the result of the second hard decision read operation is:
performing a third hard decision read operation using a fourth vol

Assignees

• Jang Joonsuc
• Yoon Sangyong
• Samsung Electronics Co Ltd

Inventors

• Jang Joonsuc
• Yoon Sangyong

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title