Magnetoresistive random access memory

Patent metadata

Field	Value
Publication number	US-9293183-B2
Application number	US-201213572017-A
Country	US
Kind code	B2
Filing date	Aug 10, 2012
Priority date	Aug 11, 2011
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A magnetoresistive random access memory includes a memory cell line in which memory cells are formed and write bit lines. The memory cell line 1 includes a magnetic recording layer, magnetization fixed layers, reference layers, spacer layers, and nMOS transistors. The spacer layer and the reference layer are located between the magnetization fixed layer and the magnetization fixed layer). The magnetization fixed layers have a magnetization fixed to a direction opposite to that of a magnetization of the magnetization fixed layers. The reference layers also have a fixed magnetization direction. The nMOS transistor is provided between the write bit line and the magnetization fixed layer.

First claim

What is claimed is:

1. A magnetoresistive random access memory comprising:
a first memory cell line in which first to Nth memory cells (N is an integer greater than or equal to 2) are formed; and
first to (N+1)th write bit lines,
wherein the first memory cell line includes
a magnetic recording layer formed of a ferromagnetic body,
first to (N+1)th magnetization fixed layers coupled to the magnetic recording layer,
first to Nth reference layers provided to face the magnetic recording layer,
first to Nth non-magnetic spacer layers inserted between the magnetic recording layer and the first to the Nth reference layers, respectively, and
first to (N+1)th transistors,
the ith reference layer (i ranges from 1 to N) and the ith spacer layer are located between the ith and the (i+1)th magnetization fixed layers,
odd-numbered magnetization fixed layers among the first to the (N+1)th magnetization fixed layers have a magnetization fixed to a first direction,
even-numbered magnetization fixed layers among the first to the (N+1)th magnetization fixed layers have a magnetization fixed to a second direction opposite to the first direction,
the first to the Nth reference layers have a magnetization fixed to the first direction or the second direction, and
the ith transistor is provided between the ith write bit line and the ith magnetization fixed layer,
wherein data is written to the ith memory cell by flowing a write current between the ith write bit line and the (i+1)th write bit line through the ith and the (i+1)th transistors, and
wherein data is written to the jth memory cell (j is an integer greater than or equal to 1 and smaller than or equal to N) by turning on the first to the (N+1)th transistors and then applying a first potential to the first write bit line when j=1, applying the first potential to the first to the jth write bit lines when j>1, applying a second potential different from the first potential to the (N+1)th write bit line when j=N, and applying the second potential to the (j+1)th to the (N+1)th write bit lines when j<N.

2. The magnetoresistive random access memory according to claim 1 , wherein
data is read from the kth memory cell (k is an integer greater than or equal to 1 and smaller than or equal to N) by turning on the first to the (N+1)th transistors, applying a third potential to the first to the Nth write bit lines, and applying a fourth potential different from the third potential to the kth reference layer.

3. The magnetoresistive random access memory according to claim 1 , further comprising:
a write circuit that applies potentials to the first to the (N+1)th write bit lines responding to an address and write data,
wherein, when the jth memory cell is selected by the address, the write circuit applies the first potential to the first to the jth write bit lines and applies the second potential to the (j+1)th to the (N+1)th write bit lines.

4. The magnetoresistive random access memory according to claim 3 , further comprising:
a read circuit that reads data of the first to the Nth memory cells,
wherein, when the write circuit writes a first data, which is one of data “0” and data “1”, to any one of the first to the Nth memory cell, the write circuit applies potentials to the first to the Nth write bit lines so that the write current flows through the magnetic recording layer in a third direction, and when the write circuit writes a second data, which is the other one of data “0” and data “1”, to any one of the first to the Nth memory cell, the write circuit applies potentials to the first to the Nth write bit lines so that the write current flows through the magnetic recording layer in a fourth direction opposite to the third direction,
when the read circuit reads data of an odd-numbered memory cell of the first to the Nth memory cells, if a current flowing through the odd-numbered memory cell is larger than a reference current, the read circuit determines that the data stored in the odd-numbered memory cell is a third data, which is one of data “0” and data “1”, and if the current is smaller than the reference current, the read circuit determines that the data is a fourth data, which is the other one of data “0” and data “1”, and
when the read circuit reads data of an even-numbered memory cell of the first to the Nth memory cells, if a current flowing through the even-numbered memory cell is larger than a reference current, the read circuit determines that the data stored in the even-numbered memory cell is the fourth data, and if the current is smaller than the reference current, the read circuit determines that the data is the third data.

5. A magnetoresistive random access memory comprising:
a plurality of memory arrays, each of which includes a memory cell line in which first to Nth memory cells are formed (N is an integer greater than or equal to 2) and first to (N+1)th write bit lines; and
a read circuit,
wherein the memory cell line includes
a magnetic recording layer formed of a ferromagnetic body,
first to (N+1)th magnetization fixed layers coupled to the magnetic recording layer,
first to Nth reference layers provided to face the magnetic recording layer,
first to Nth non-magnetic spacer layers inserted between the magnetic recording layer and the first to the Nth reference layers, respectively, and
first to (N+1)th transistors,
the ith reference layer (i ranges from 1 to N) and the ith spacer layer are located between the ith and the (i+1)th magnetization fixed layers,
the first to the Nth reference layers have a magnetization fixed to a first direction or a second direction opposite to the first direction,
the ith transistor is provided between the ith write bit line and the ith magnetization fixed layer,
in the memory cell line of a first memory array of the plurality of memory arrays, odd-numbered magnetization fixed layers among the first to the (N+1)th magnetization fixed layers have a magnetization fixed to the first direction and even-numbered magnetization fixed layers among the first to the (N+1)th magnetization fixed layers have a magnetization fixed to the second direction, and
in the memory cell line of a second memory array of the plurality of memory arrays, odd-numbered magnetization fixed layers among the first to the (N+1)th magnetization fixed layers have a magnetization fixed to the second direction and even-numbered magnetization fixed layers among the first to the (N+1)th magnetization fixed layers have a magnetization fixed to the first direction,
wherein the magnetic recording layer of the memory cell line of the first memory array and the magnetic recording layer of the memory cell line of the second memory array are integrally formed into one body,
wherein a dummy cell including a reference layer having a fixed magnetization and a non-magnetic spacer layer is provided at a position in the magnetic recording layer between the first memory array and the second memory array, and
wherein each of the first and the second memory arrays includes a reference cell line having the same configuration as that of the memory cell line,
the magnetic recording layer of the reference cell line of the first memory array and the magnetic recording layer of the reference cell line of the second memory array are integrally formed into one body,
a first reference cell including a reference layer having a fixed magnetization and a non-magnetic spacer layer is provided at a position in the magnetic recording layer adjacent to the first memory array,
a second reference cell including a reference layer having a fixed magnetization and a non-magnetic spacer layer is provided at a position in the magnetic recording layer adjacent to the second memory array, and
the read circuit generates a reference current from a current flowing through th

Assignees

• Suzuki Kazumasa
• Renesas Electronics Corp

Inventors

• Suzuki Kazumasa

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/15 Primary

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title