Configurable bandwidth memory devices and methods

US9293170B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9293170-B2
Application numberUS-201314136925-A
CountryUS
Kind codeB2
Filing dateDec 20, 2013
Priority dateMar 23, 2009
Publication dateMar 22, 2016
Grant dateMar 22, 2016

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Abstract

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Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

First claim

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What is claimed is: 1. A memory device, comprising: a stack of memory dies, including a number of memory portions; a logic die coupled to the stack of memory dies; a memory fabric control register selectably coupled to the number of memory portions to select a number of memory portions that operate synchronously for a single memory request; wherein each memory portion includes both a direct connection to an originating and/or destination device, and a buffered connection to…

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What does patent US9293170B2 cover?
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G11C5/02. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).