Display having vertical gate line extensions and minimized borders

Patent metadata

Field	Value
Publication number	US-9293102-B1
Application number	US-201414504215-A
Country	US
Kind code	B1
Filing date	Oct 1, 2014
Priority date	Oct 1, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

First claim

What is claimed is:

1. A display, comprising:
rows and columns of pixels, each pixel having at least one transistor with a gate;
a plurality of gate lines each of which is connected to the gates of the transistors in the pixels of a respective one of the rows;
a plurality of data lines running perpendicular to the gate lines;
a plurality of gate line extensions each of which runs parallel to the data lines and each of which is connected to a respective one of the gate lines, wherein each gate line extension runs under a respective one of the data lines and is separated from that gate line by a layer of dielectric, wherein the plurality of gate line extensions are all of equal length;
a layer of liquid crystal material;
electrodes coupled to the transistors, wherein the transistors apply voltages to the electrodes that create electric fields in the layer of liquid crystal material; and
vias that connect the gate lines extensions to the gate lines.

2. A display, comprising:
an array of pixels organized in rows and columns;
a plurality of horizontally extending gate lines each of which is associated with a respective one of the rows of pixels;
a plurality of vertically extending data lines each of which is associated with a respective one of the columns of pixels;
a plurality of vertically extending gate line extensions each of which is associated with a respective one of the columns of pixels and each of which is connected to a respective one of the horizontally extending gate lines so that gate line signals are provided from the vertically extending gate line extensions to the horizontally extending gate lines; and
a plurality of vias, wherein each vertically extending gate line extension is connected to its respective horizontally extending gate line with a respective one of the plurality of vias.

3. The display defined in claim 2 further comprising:
a substrate having four edges; and
display driver circuitry mounted along a given one of the four edges, wherein the display driver circuitry supplies image data signals to the data lines and gate line signals to the vertically extending gate line extensions.

4. The display defined in claim 3 wherein the display driver circuitry includes gate driver circuitry and wherein the gate driver circuitry supplies the gate line signals to the vertically extending gate line extensions.

5. The display defined in claim 3 wherein the substrate comprises a glass layer and wherein the display driver circuitry includes at least some thin-film transistor circuitry on the glass layer.

6. The display defined in claim 5 further comprising:
an additional substrate; and
a layer of liquid crystal material between the substrate and the additional substrate.

7. The display defined in claim 6 wherein each pixel comprises a thin-film transistor.

8. The display defined in claim 7 wherein each pixel further comprises an electrode that supplies an electric field to a portion of the layer of liquid crystal material.

9. The display defined in claim 8 wherein the horizontally extending gate line in each row of pixels has a gate line protrusion that is connected to the via in that row.

10. The display defined in claim 9 wherein each via is located in one of the columns and wherein the vertically extending gate line extension in each column has a protrusion that is connected to the via in that column.

11. The display defined in claim 10 wherein the each vertically extending gate line extension runs under a respective one of the vertically extending data lines.

12. The display defined in claim 11 wherein the vertically extending gate line extensions are all equal in length.

13. The display defined in claim 2 wherein the vertically extending gate line extension and vertically extending data line in each column overlap.

14. The display defined in claim 2 wherein the vertically extending gate line extension in each column runs under the vertically extending data line in that column.

15. A display, comprising:
a plurality of pixels each of which has a transistor with a transistor gate and first and second source-drain terminals;
a first plurality of lines that supply gate control signals to the transistor gates;
a second plurality of lines that run perpendicular to the first plurality of lines and that supply data signals to the first source-drain terminals; and
a third plurality of lines each of which is connected to a respective via to a respective one of the first plurality of lines and runs parallel to the second plurality of lines under a respective one of the second plurality of lines.

16. The display defined in claim 15 further comprising:
a layer of liquid crystal material; and
an electrode in each of the plurality of pixels that supplies an electric field to a portion of the layer of liquid crystal material, wherein the electrode in each pixel is coupled to the transistor in that pixel.

Assignees

• Apple Inc
• Apple Inc

Inventors

• Chiu Hao-Lin
• Yang Byung Duk
• Huang Chun-Yao
• Kim Kyung Wook
• Chang Shih Chang
• Lee Szu-Hsien

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G02F1/1345 Primary

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• G09G3/3666 Primary

  with the matrix divided into sections · CPC title

• G06F2203/04104

  Multi-touch detection in digitiser, i.e. details about the simultaneous detection of a plurality of touching locations, e.g. multiple fingers or pen and finger · CPC title