Semiconductor memory device with operation functions to be used during a modified read or write mode

Patent metadata

Field	Value
Publication number	US-9292425-B2
Application number	US-201313966585-A
Country	US
Kind code	B2
Filing date	Aug 14, 2013
Priority date	Sep 11, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a read circuit configured to read data from selected memory cells in the memory cell array;
a write circuit configured to write data into selected memory cells in the memory cell array;
an operation unit configured to perform an operation on read data obtained by the read circuit according to operation assignment information applied through an address line when entering a modified read mode; and
a control circuit configured to manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit into the selected memory cells in the modified read mode,
wherein during the modified read mode, a second input address identifying an operator and indicating an address storing a second operand is received after a first input address indicating an address storing a first operand to be applied to the operation unit,
wherein the second input address comprises a first part that identifies the operator and a second other part that indicates the address storing the second operand, and the second part is a column offset with respect to the first input address.

2. The semiconductor memory device as set forth in claim 1 , wherein a read-operate-write operation is performed internally within the semiconductor memory device in response to a single request from an external source.

3. The semiconductor memory device as set forth in claim 1 , wherein entering the modified read mode is accomplished using one of mode register set timing, fuse programming, NVM programming, and bonding options.

4. The semiconductor memory device as set forth in claim 1 , wherein the operation result data is directly written into memory cells indicating the first input address or is written into memory cells spaced apart from the second input address as far as the column offset.

5. The semiconductor memory device as set forth in claim 1 , wherein the operation result data is directly written into memory cells indicated by the first input address, is written into memory cells indicated by part of the second input address, or is written into an internal register of the semiconductor memory device.

6. The semiconductor memory device as set forth in claim 5 , wherein data output to an external entity through the read circuit is the read data or the operation result data.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Hyojin
• Park Chulwoo
• Kang Uksong
• Yu Haksoo

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title