Software enabled and disabled coalescing of memory transactions

Patent metadata

Field	Value
Publication number	US-9292357-B2
Application number	US-201514854707-A
Country	US
Kind code	B2
Filing date	Sep 15, 2015
Priority date	Dec 12, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.

First claim

What is claimed is:

1. A method of controlling a coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method for generating optimized machine instructions based on an intermediate representation of a program, the method comprising:
based on the intermediate representation, generating, by a processor, a first module of optimized non-transactional machine instructions;
based on the intermediate representation identifying two atomic tasks to be performed, the two atomic tasks consisting of a first atomic task and a second atomic task, determining whether the two atomic tasks are to be coalesced into a single atomic task;
based on determining that the two atomic tasks are not to be coalesced, generating for the first atomic task, a first transaction of transactional machine instructions to be executed and generating for the second atomic task, a second transaction of transactional machine instructions to be executed; and
based on determining that the two atomic tasks are to be coalesced, generating for the two atomic tasks, a single coalesced transaction of transactional machine instructions to be executed.

2. The method according to claim 1 , wherein the method for generating optimized machine instructions is performed by a just-in-time (JIT) compiler.

3. The method according to claim 1 , further comprising:
executing a run-time instrumentation program on a previous instance of a previous transaction comprising of any one of said single coalesced transaction, said first transaction and said second transaction to determine whether the two atomic tasks are to be coalesced.

4. The method of claim 3 , wherein executing the run-time instrumentation program includes:
generating an environment for run-time profiling of the previous instance of the previous transaction for obtaining instrumentation information; and
profiling the execution of the previous instance of the previous transaction using obtained instrumentation information; and
based on the profiling, changing run-time environment of the program.

5. The method of claim 4 , the method further comprising:
processing a run-time instrumentation directive of the run-time instrumentation program; and
configuring a control of a run-time instrument based, at least in part, on the processed run-time instrumentation directive, wherein the run-time instrumentation program includes one or more instructions to obtain instrumentation information regarding the execution of transactions of the program.

6. The method of claim 3 , wherein the run-time instrumentation program modifies continued execution of the program, the modifying including adding one or more coalescing instructions to the associated program to control coalescing of transactions based, at least in part, on an analysis of gathered instrumentation information.

7. The method of claim 5 , wherein the one or more coalescing instructions include one or more of: (i) an instruction to coalesce outermost transactions, (ii) an instruction to remove a transaction begin or end instruction or to not execute a transaction begin or end instruction, (iii) an instruction to modify a transaction begin or end instruction such that an associated outermost transaction can-not be coalesced with a type of outermost transaction if a number of already coalesced instructions is greater than a threshold, (iv) an instruction to indicate that a particular outermost transaction is not-to-be coalesced with a type of outermost transaction if the number of already coalesced instructions is greater than the threshold, (v) an instruction to process non-transactional instructions as transactional instructions, (vi) an instruction to cease coalescing outermost transactions, and (vii) an instruction to specify a maximum allowable number of coalesced outermost transactions, the method further comprising:
executing a run-time instrumentation program on a previous instance of a previous transaction including one or more of said single coalesced transaction, said first transaction and said second transaction to determine whether the two atomic tasks are to be coalesced.

8. The method of claim 3 , wherein the determining whether the two atomic tasks are to be coalesced is based on one or more of: (i) a reason for a coalesced outermost transaction being aborted, and a number of aborts it has received, (ii) a number of instructions between two coalesced outermost transactions, (iii) a type of instruction between two coalesced outermost transactions, (iv) whether any of the instructions between two coalesced outermost transactions are restricted from running in a given outermost transaction, (v) a number of dynamic instructions in a given outermost transaction, and (vi) a size of a footprint of a dynamic instruction in a given outermost transaction.

Assignees

• IBM

Inventors

• Busaba Fadi
• Gschwind Michael Karl
• Salapura Valentina
• Shum Chung-Lung K

Classifications

• G06F9/526

  Mutual exclusion algorithms · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F8/443

  Optimisation · CPC title

• G06F9/528

  by using speculative mechanisms · CPC title

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title