Communication using integrated circuit interconnect circuitry

Patent metadata

Field	Value
Publication number	US-9288258-B2
Application number	US-201113825190-A
Country	US
Kind code	B2
Filing date	Oct 11, 2011
Priority date	Oct 12, 2010
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

An integrated circuit comprising multiple master units and multiple slave units connected via interconnect circuitry utilizes token based node-to-node communication flow management within the interconnect circuitry with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a plurality of master units configured to generate communication transactions;
interconnect circuitry coupled to said plurality of master units and configured to carry said communication transactions; and
one or more slave units coupled to said interconnect circuitry and configured to respond to said communication transactions; wherein
said interconnect circuitry is configured to provide a plurality of virtual networks, each virtual network connecting at least one of said plurality of master units to at least one of said one or more slave units and including a plurality of network nodes, at least two of said plurality of virtual networks being overlapping virtual networks having an overlapped portion that shares a physical communication link between at least two of said plurality of network nodes; and
at least network nodes within said overlapped portion perform node-to-node token based communication flow management whereby:
(i) before asserting communication signals corresponding to a communication transaction with a target slave unit via one of said overlapping virtual networks, at least network nodes within said overlapped portion are configured to assert a token request upon said overlapping virtual network to request a token signal for said overlapping virtual network from a next network node downstream within said overlapping virtual network toward said target slave unit and not to assert said communication signals upon said physical communication link shared with another overlapping virtual network until said token signal is received; and
(ii) said next network node receiving said token request blocks return of said token signal until said next network node is ready to receive said communication signals.

2. An integrated circuit as claimed in claim 1 , wherein said next network node is ready to receive said communication signals when one of:
(i) said next network node is able to store said communication signal and to trigger clearing of said communication signals from said overlapped portion such that said physical communication link shared with another overlapping virtual network is made available for further use; and
(ii) said next network node has received a token signal from a further network node downstream within said overlapping virtual network indicating said further network node is ready to receive said communication signals.

3. An integrated circuit as claimed in claim 1 , wherein a master unit within said overlapping virtual network is one of said network nodes and generates said token request.

4. An integrated circuit as claimed in claim 3 , wherein a network node within said overlapping virtual network between said master unit and said target slave unit forwards said token request toward said slave unit.

5. An integrated circuit as claimed in claim 1 , wherein a network node within said overlapping virtual network between said master unit and said target slave unit includes storage elements configured to store said communication signals, said network node responding to receipt of said token request to return said token signal if said storage elements are available to store said communication signals within said storage elements.

6. An integrated circuit as claimed in claim 5 , wherein network nodes within said overlapped portion include a plurality of sets of storage elements each dedicated to storing communication signals for a respective overlapping virtual network.

7. An integrated circuit as claimed in claim 6 , wherein token requests and token signals passing between said network nodes within said overlapped portion are pipeline processed.

8. An integrated circuit as claimed in claim 1 , wherein said token request and said token signal provide handshake communication control.

9. An integrated circuit as claimed in claim 1 , wherein said target slave unit within said overlapping virtual network is one of said network nodes and generates said token signal when ready to receive said communication signals.

10. An integrated circuit as claimed in claim 1 , wherein congestion upon one of said overlapping virtual networks that blocks return of said token signal does not block communication via said another overlapping virtual network.

11. An integrated circuit as claimed in claim 1 , wherein a graphics processing unit and a general purpose processor are master units connected via different overlapping virtual networks to a memory controller being a slave device.

12. An integrated circuit as claimed in claim 1 , comprising respective overlapping virtual networks for carrying write address signals and for carrying write data.

13. An integrated circuit as claimed in claim 12 , wherein at least network nodes asserting a token request upon an overlapping virtual network for carrying write address signals also assert a token request upon an overlapping virtual network for carrying corresponding write data signals.

14. An integrated circuit as claimed in claim 13 , wherein if said communication transaction is a write burst request having a plurality of write data beats, then a token request is asserted for each of said write data beats.

15. An integrated circuit as claimed in claim 13 , wherein in response to a sequence of communication transactions token signals for said write data signals are returned in a same order with respect to said sequence as token signals for said write address signals.

16. An integrated circuit as claimed in claim 1 , wherein at least one of said plurality of master units is a token-pre-fetching master unit configured to issue a token request before a corresponding communication transaction is ready to issue, thereby reducing latency associated with said communication transaction.

17. An integrated circuit as claimed in claim 16 , wherein a network node configured to receive a token request from a token-pre-fetching master unit includes at least one set of storage elements dedicated to storing communication signals for said token-pre-fetching master unit.

18. An integrated circuit as claimed in claim 17 , wherein a token-pre-fetching master unit can pre-fetch a maximum of one token signal.

19. An integrated circuit as claimed in claim 1 , comprising a plurality of slave units connected to said overlapped portion.

20. An integrated circuit as claimed in claim 19 , wherein a final network node within said overlapped portion and connected to said plurality of slave units uses a memory address associated with said communication transaction to route said token request to one of said slave units mapped to said memory address.

21. An integrated circuit as claimed in claim 20 , wherein said final network node issues separate token requests to each of said plurality of slave units an receives separate token signals from each of said plurality of slave units.

22. An integrated circuit as claimed in claim 1 , wherein said communication transactions have an associated priority value and network nodes within said overlapped portion are responsive to priority values associated with different communication transactions to arbitrate access to said physical communication link.

23. An integrated circuit comprising:
a plurality of master means for generating communication transactions;
interconnect means for carrying said communication transactions, said interconnect means being coupled to said plurality of master means; and
one or more slave means for responding to said comm

Assignees

• Mace Timothy Charles
• Rose Andrew Christopher
• Advanced Risc Mach Ltd

Inventors

• Mace Timothy Charles
• Rose Andrew Christopher

Classifications

• G06F1/22

  Means for limiting or controlling the pin/gate ratio · CPC title

• G06F15/7842

  on one IC chip (single chip microcontrollers) · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• H04L12/40084

  Bus arbitration · CPC title