Time synchronization message conversion
US-12160498-B1 · Dec 3, 2024 · US
US9288037B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9288037-B2 |
| Application number | US-201113825532-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 1, 2011 |
| Priority date | Sep 24, 2010 |
| Publication date | Mar 15, 2016 |
| Grant date | Mar 15, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method for time synchronization in a communications network having multiple nodes, wherein the nodes comprise a first node and at least one second node, where the first node generates first cycle counter states according to a reference clock frequency and the second node or nodes each generate second cycle counter states according to an internal clock frequency, where a time synchronization is carried out in sequential synchronization cycles, in which synchronization messages originating from the first node are sequentially transmitted from one node to another node, and a synchronization message transmitted by a node contains information used for time synchronization in the at least one second node receiving the synchronization message such that a time synchronization is performed in a given second node based on an estimation of a first cycle counter state and a compensation factor in combination with a linear quadratic regulator.
Opening claim text (preview).
The invention claimed is: 1. A method for time synchronization in a communications network having a first node and at least one second node, comprising: i) sending, within a synchronization cycle, a synchronization message from the first node to the at least one second node; and ii) providing, by the first node, a first cycle counter state in accordance with a reference clock frequency and providing, by a respective second node of the at least one second node, a second cycle counter state in accordance with an internal clock frequency; wherein time synchronization of the respective second node of the at least one second node is implemented such that: (a) the synchronization message is received at the respective second node; (b) an estimated first cycle counter state and an estimated compensation factor are estimated for a measured second cycle counter state of the respective second node based on information contained in the received synchronization message by a stochastic state estimator, the estimated first cycle counter state estimating the first cycle counter state of the first node for a point in time at which the synchronization message is received by the respective second node, and the estimated compensation factor estimating a duty cycle ratio of the reference clock frequency to a respective internal clock frequency for the synchronization cycle; (c) a linear-quadratic regulator is utilized to determine from both the estimated first cycle counter state and the estimated compensator factor a controlled first cycle counter state and a controlled compensation factor based on a controlled system which contains a correction term for the controlled compensation factor as a control variable, the controlled compensation factor estimating a duty cycle ratio of the reference clock frequency to the respective internal clock frequency, and the controlled first cycle counter state indicating a synchronized timing; and (d) a two-dimensional model is utilized for the stochastic state estimator and the linear-quadratic regulator, the two-dimensional model comprising the estimated first cycle counter and the estimated compensation factor as states. 2. The method in accordance with claim 1 , wherein, in step b), a variation of the compensation factor based on a stochastic process is modeled. 3. The method in accordance with claim 1 , wherein the control variable is updated after each receipt of the synchronization message in the respective second node and supplied to a control loop. 4. The method in accordance with claim 2 , wherein the control variable is updated after each receipt of the synchronization message in the respective second node and supplied to a control loop. 5. The method in accordance with claim 3 , wherein the control loop for the linear-quadratic regulator at a time of receipt of the synchronization message in a kth synchronization cycle in an nth second node and immediately before an updating of the manipulating variable is in accordance with the following relationship: [ CT n ( k ) o n ( k ) ] = A n ( k - 1 ) [ CT n ( k - 1 ) o n ( k - 1 ) ] + [ 0 1 ] · u n s ( k - 1 ) ; where CT n (k) is the regulated first cycle counter state at the time of receipt of the synchronization message in the kth synchronization cycle; where o n (k) is the regulated compensation factor at the time of receipt of the synchronization message in the kth synchronization cycle; where u n s (k−1) is a correction term for the regulated compensation factor used in a kth synchronization cycle; where A n ( k
Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title
Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title
using intermediate nodes, e.g. modification of a received timestamp before further transmission to the next packet node, e.g. including internal delay time or residence time into the packet · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.