PVT compensation scheme for output buffers

Patent metadata

Field	Value
Publication number	US-9287872-B2
Application number	US-201414308747-A
Country	US
Kind code	B2
Filing date	Jun 19, 2014
Priority date	Jun 19, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.

First claim

What is claimed is:

1. A method for calibrating buffers in an integrated circuit, the method comprising:
(a) applying a selected source-current level to a first pull-down buffer at a first node;
(b) adjusting drive-strength level of the first pull-down buffer until a first voltage at the first node reaches a first reference voltage level to determine a N-type calibration setting for the first pull-down buffer;
(c) applying the N-type calibration setting to a second pull-down buffer connected to a first pull-up buffer at a second node; and
(d) adjusting drive-strength level of the first pull-up buffer until a second voltage at the second node reaches a second reference voltage level to determine a P-type calibration setting for the first pull-up buffer.

2. A The invention of claim 1 , wherein:
the integrated circuit has (i) a single instance of the first pull-down buffer and (ii) a different instance of the second pull-down buffer and a different instance of the first pull-up buffer for each different bank in the integrated circuit;
the N-type calibration setting is applied to one or more on-line pull-down buffers in the integrated circuit; and
for one or more banks, the P-type calibration setting is applied to one or more on-line pull-up buffers in the bank.

3. A The invention of claim 1 , further comprising:
(e) selecting a different source-current level and repeating steps (b)-(d) to determine N-type and P-type calibration settings for the first pull-down buffer and the first pull-up buffer, respectively, for the different source-current level.

4. A The invention of claim 1 , wherein:
step (b) comprises:
(b1) adjusting the drive-strength level of the first pull-down buffer until the first voltage at the first node reaches the first reference voltage level multiple times; and
(b2) averaging pull-down buffer results from the multiple times to determine the N-type calibration setting for the first pull-down buffer; and

step (d) comprises:
(d1) adjusting the drive-strength level of the first pull-up buffer until the second voltage at the second node reaches the second reference voltage level multiple times; and
(d2) averaging pull-up buffer results from the multiple times to determine the P-type calibration setting for the first pull-up buffer.

5. A The invention of claim 4 , wherein steps (b1) and (d1) respectively comprise changing directions of changes in the drive-strength levels between successive pull-down and pull-up buffer results.

6. A The invention of claim 1 , wherein the N-type and P-type calibration settings are determined without using any input/output pins of the integrated circuit to connect the first and second pull-down buffers and the first pull-up buffer to any external resistors.

7. A The invention of claim 1 , further comprising:
(e) selecting a different source-current level and repeating steps (b)-(d) to determine N-type and P-type calibration settings for the first pull-down buffer and the first pull-up buffer, respectively, for the different source-current level, wherein:
the integrated circuit has (i) a single instance of the first pull-down buffer and (ii) a different instance of the second pull-down buffer and a different instance of the first pull-up buffer for each different bank in the integrated circuit;
the N-type calibration setting is applied to one or more on-line pull-down buffers in the integrated circuit;
for one or more banks, the P-type calibration setting is applied to one or more on-line pull-up buffers in the bank;
step (b) comprises:
(b1) adjusting the drive-strength level of the first pull-down buffer until the first voltage at the first node reaches the first reference voltage level multiple times; and
(b2) averaging pull-down buffer results from the multiple times to determine the N-type calibration setting for the first pull-down buffer; and

step (d) comprises:
(d1) adjusting the drive-strength level of the first pull-up buffer until the second voltage at the second node reaches the second reference voltage level multiple times; and
(d2) averaging pull-up buffer results from the multiple times to determine the P-type calibration setting for the first pull-up buffer, wherein steps (b1) and (d1) respectively comprise changing directions of changes in the drive-strength levels between successive pull-down and pull-up buffer results; and

the N-type and P-type calibration settings are determined without using any input/output pins of the integrated circuit to connect the first and second pull-down buffers and the first pull-up buffer to any external resistors.

8. An integrated circuit comprising:
pull-down calibration circuitry comprising:
a first pull-down buffer;
a programmable current source connected to apply a selected source-current level to the first pull-down buffer at a first node;
a first voltage reference source configured to generate a first reference voltage;
a first differential comparator configured to compare a first voltage at the first node to the first reference voltage; and
a first controller configured to adjust drive-strength level of the first pull-down buffer until the first voltage at the first node reaches the first reference voltage level to determine an N-type calibration setting for the first pull-down buffer; and

pull-up calibration circuitry comprising:
a second pull-down buffer to which the N-type calibration setting is applied;
a first pull-up buffer connected to the second pull-down buffer at a second node;
a second voltage reference source configured to generate a second reference voltage;
a second differential comparator configured to compare a second voltage at the second node to the second reference voltage; and
a second controller configured to adjust drive-strength level of the first pull-up buffer until the second voltage at the second node reaches the second reference voltage level to determine a P-type calibration setting for the first pull-up buffer.

9. The invention of claim 8 , wherein:
the integrated circuit has (i) a single instance of the first pull-down buffer and (ii) a different instance of the second pull-down buffer and a different instance of the first pull-up buffer for each different bank in the integrated circuit;
the N-type calibration setting is applied to one or more on-line pull-down buffers in the integrated circuit; and
for one or more banks, the P-type calibration setting is applied to one or more on-line pull-up buffers in the bank.

10. The invention of claim 8 , wherein:
the first controller is configured to (i) select a different source-current level and (ii) adjust the drive-strength level of the first pull-down buffer until the first voltage at the first node reaches the first reference voltage level to determine an other N-type calibration setting for the first pull-down buffer corresponding to the different source-current level, wherein the other N-type calibration setting is applied to the second pull-down buffer; and
the second controller is configured to adjust the drive-strength level of the first pull-up buffer until the second voltage at the second node reaches the second reference voltage level to determine an other P-type calibration setting for the first pull-up buffer corresponding to the different source-current level.

11. The invention of claim 8 , wherein:
the first controller is configured to:
(1) adjust the drive-strength level of the first pull-down buffer until the first voltage at the first node reaches the first reference voltage level multiple times; and
(2) average pull-down buffer results from the multiple times to determine the N-type calibration setting for the first pull-down buffer; and

Assignees

• Lattice Semiconductor Corp
• Latticesemiconductorcorporation

Inventors

• Kee Siak Chon
• Tran Giap
• Sharpe-Geisler Brad

Classifications

• G05F1/463

  Sources providing an output which depends on temperature · CPC title

• H03K19/018514 Primary

  with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence) · CPC title

• G05F1/462

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title