LED submount with integrated interconnects

Patent metadata

Field	Value
Publication number	US-9287468-B2
Application number	US-201414549904-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 22, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A submount for light emitting diode (LED) die includes a substrate containing a plurality of tubs configured to receive an LED die, and a plurality of integrated interconnects integrated into the substrate. At least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount.

First claim

What is claimed is:

1. A submount for light emitting diode (LED) die, comprising:
a substrate comprising a plurality of tubs configured to receive an LED die; and
a plurality of integrated interconnects integrated into the substrate,
wherein at least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount.

2. The submount of claim 1 , wherein the submount allows electrical connection of LED die in series or in parallel or a combination of series and parallel by outside leads to the exposed portion of the interconnects on the side of the submount.

3. The submount of claim 1 , further comprising a first metal layer in the tubs, the first metal layer configured to form a eutectic bond with a second metal layer on an LED die when heated.

4. The submount of claim 1 , wherein the submount comprises a plurality of interconnect levels located at different depths within the submount.

5. The submount of claim 1 , further comprising a plurality of conductive filled vias connecting a first set of the plurality of integrated interconnects buried in the submount to a second set of plurality of integrated interconnects on a surface of the submount.

6. The submount of claim 5 , wherein the submount comprises a semiconducting silicon substrate and a dielectric layer located between the conductive filled vias and the semiconducting silicon substrate.

7. The submount of claim 6 , further comprising one or more barrier layers on the surface of the dielectric layer.

8. The submount of claim 4 , wherein:
the submount comprises a first buried interconnect level, a second buried interconnect level and a third buried interconnect level; and
the first buried interconnect level is associated with an LED die emitting light having a first color, the second buried interconnect level is associated with an LED die emitting light having a second color and the third buried interconnect level is associated with an LED die emitting light having a third color.

9. The submount of claim 1 , wherein the plurality of tapered tubs comprise a taper angle θbetween 75 and 89 degrees and wherein the plurality of integrated interconnects have a width between 0.1 and 10 μm.

10. A light emitting array comprising the submount of claim 1 , a plurality of LED die mounted in the submount and a plurality of the outside leads, wherein each of the plurality of the outside leads is electrically connected to the exposed portion of one of the plurality of the interconnects on the side of the submount to allow independent addressing of the plurality of LED die.

Assignees

• Glo Ab

Inventors

• Herner Scott Brad
• Romano Linda
• Thompson Daniel Bryce
• Schubert Martin

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10H20/819

  characterised by their shape, e.g. curved or truncated substrates · CPC title

• H10H20/0364

  of interconnections · CPC title