Semiconductor device and method of fabricating same

US9287397B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9287397-B2
Application numberUS-201313947911-A
CountryUS
Kind codeB2
Filing dateJul 22, 2013
Priority dateNov 23, 2012
Publication dateMar 15, 2016
Grant dateMar 15, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a semiconductor device, comprising: forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate; forming spacers on sidewalls of the gate electrodes; depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers; selectively etching the interconnection layer, wherein at least a portion of the interconnection…

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What does patent US9287397B2 cover?
A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and th…
Who is the assignee on this patent?
Semiconductor Mfg Int Corp, Semiconductor Mfg Int Shanghai
What technology area does this patent fall under?
Primary CPC classification H10W20/0698. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).