Memory device comprising a transistor including an oxide semiconductor and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-9287370-B2
Application number	US-201313772530-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Mar 2, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A memory device consumes low power, has high capacity, and is shared by a plurality of processors. A data write transistor of a memory device is manufactured with a material capable of achieving a sufficiently low off-state current of a transistor (e.g., an oxide semiconductor material that is a wide band gap semiconductor). The memory device has a memory cell including at least one data write transistor, at least one data storage transistor, and at least two data read transistors.

First claim

What is claimed is:

1. A memory device comprising:
a first transistor including a first channel formation region;
a second transistor including a second channel formation region;
a third transistor including a third channel formation region;
a fourth transistor including a fourth channel formation region;
a first line;
a second line;
a third line;
a fourth line;
a fifth line;
a sixth line; and
a seventh line,
wherein one of a source and a drain of the first transistor is electrically connected to the first line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line,
wherein one of a source and a drain of the third transistor is electrically connected to the third line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth line,
wherein a gate of the first transistor is electrically connected to the fifth line,
wherein a gate of the third transistor is electrically connected to the sixth line,
wherein a gate of the fourth transistor is electrically connected to the seventh line,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor so that a node is formed,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor,
wherein the first channel formation region includes a semiconductor material that is different from a semiconductor material in the second channel formation region, the third channel formation region and the fourth channel formation region, and
wherein the first channel formation region includes an oxide semiconductor.

2. The memory device according to claim 1 , further comprising:
a capacitor; and
an eighth line;
wherein one electrode of the capacitor is electrically connected to the node, and
wherein the other electrode of the capacitor is electrically connected to the eighth line.

3. The memory device according to claim 1 ,
wherein the memory device is configured to store electric charge in the node when the first transistor is in an off state.

4. The memory device according to claim 1 ,
wherein the second channel formation region, the third channel formation region and the fourth channel formation region contain single crystal silicon.

5. The memory device according to claim 2 ,
wherein the first line is a write data line,
wherein the second line is a first power supply line,
wherein the third line is a first read data line,
wherein the fourth line is a second read data line,
wherein the fifth line is a write selection line,
wherein the sixth line is a first read selection line,
wherein the seventh line is a second read selection line, and
wherein the eighth line is a second power supply line.

6. A semiconductor device comprising the memory device according to claim 1 , the semiconductor device further comprising:
a first processor;
a second processor; and
a selector,
wherein the first processor is configured to write data to the memory device using the fifth line and the first line through the selector at a first timing,
wherein the second processor is configured to write data to the memory device using the fifth line and the first line through the selector at a second timing that is different from the first timing,
wherein the first processor is configured to read data of the memory device using the sixth line and the third line, and
wherein the second processor is configured to read data of the memory device using the seventh line and the fourth line.

7. The memory device according to claim 1 ,
wherein the first channel formation region contains indium, gallium and zinc.

8. An electric device comprising the memory device according to claim 1 .

9. A memory device comprising:
a first transistor including a first channel formation region;
a second transistor including a second channel formation region;
a third transistor including a third channel formation region;
a fourth transistor including a fourth channel formation region;
a fifth transistor including a fifth channel formation region;
a first line;
a second line;
a third line;
a fourth line;
a fifth line;
a sixth line;
a seventh line;
an eighth line; and
a ninth line,
wherein one of a source and a drain of the first transistor is electrically connected to the first line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line,
wherein one of a source and a drain of the third transistor is electrically connected to the third line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the eighth line,
wherein a gate of the first transistor is electrically connected to the fifth line,
wherein a gate of the third transistor is electrically connected to the sixth line,
wherein a gate of the fourth transistor is electrically connected to the seventh line,
wherein a gate of the fifth transistor is electrically connected to the ninth line,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the fifth transistor are electrically connected to a gate of the second transistor so that a node is formed,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor,
wherein the first channel formation region includes a semiconductor material different from a semiconductor material in the second channel formation region, the third channel formation region and the fourth channel formation region,
wherein the first channel formation region includes an oxide semiconductor, and
wherein the fifth channel formation region includes an oxide semiconductor.

10. The memory device according to claim 9 , further comprising:
a capacitor; and
a tenth line;
wherein one electrode of the capacitor is electrically connected to the node, and
wherein the other electrode of the capacitor is electrically connected to the tenth line.

11. The memory device according to claim 9 ,
wherein the memory device is configured to store electric charge in the node when the first transistor and the fifth transistor are in an off state.

12. The memory device according to claim 9 ,
wherein the second channel formation region, the third channel formation region and the fourth channel formation region contain single crystal silicon.

13. The memory device according to claim 10 ,
wherein the first line is a first write data line,
wherein the second line is a first power supply line,
wherein the third line is a first read data line,
wherein the fourth line is a second read data line,
wherein the fifth line is a first write selection line,
wherein the sixth line is a first read selection line,
wherein the seventh line is a second read selection line,
wherein the eighth line is a second write data line,
wherein the ninth line is a second write selection line, and
wherein the tenth line is a second power supply line.

14. A semi

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title