Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9287286-B2
Application number	US-201414502776-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	May 23, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

First claim

What is claimed is:

1. A three-dimensional nonvolatile memory device, comprising:
a plurality of word lines stacked over a substrate;
a first vertical hole and a second vertical hole vertically passing through the word lines;
a first vertical channel layer formed in the first vertical hole;
a second vertical channel layer formed in the second vertical hole, wherein the second vertical channel layer is coupled to the first vertical channel layer through a pipe channel layer;
tunnel insulating layers, charge trap layers and charge blocking layers surrounding the first vertical channel layer and the second vertical channel layer in each of the first vertical hole and the second vertical hole;
a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, wherein the pad and the contact plug are vertically in alignment with the first vertical channel layer, and a width of the pad is greater than that of the first vertical hole and that of the contact plug; and
a common source line formed over the second vertical channel layer.

2. The three-dimensional nonvolatile memory device of claim 1 , wherein the first vertical channel layer and the second vertical channel layer are electrically coupled through a lower pipe channel layer.

3. The three-dimensional nonvolatile memory device of claim 1 , wherein the pad is formed between the first vertical channel layer and the contact plug.

4. The three-dimensional nonvolatile memory device of claim 1 , wherein the pad has a greater width than the contact plug.

5. The three-dimensional nonvolatile memory device of claim 1 , wherein the pad includes one of a polysilicon layer, a metal layer, and a stacked layer of a polysilicon layer and a metal layer.

6. The three-dimensional nonvolatile memory device of claim 1 , wherein the common source line electrically contacts the second vertical channel layer.

7. The three-dimensional nonvolatile memory device of claim 1 , wherein the common source line includes one of a polysilicon layer, a metal layer, and a stacked layer of a polysilicon layer and a metal layer.

8. The three-dimensional nonvolatile memory device of claim 1 , further comprising a plurality of first vertical channel layers and a plurality of second vertical channel layers.

9. The three-dimensional nonvolatile memory device of claim 8 , further comprising a plurality of pads formed in an island shape over the first vertical channel layers.

10. The three-dimensional nonvolatile memory device of claim 8 , wherein the common source line is formed in a generally linear shape over the second vertical channel layers.

11. The three-dimensional nonvolatile memory device of claim 10 , wherein the common source line extends generally in a first direction, the second vertical channel layers are arranged in the first direction, and common source line commonly contacts the second vertical channel layers.

12. The three-dimensional nonvolatile memory device of claim 1 , further comprising:
a drain selection line formed between the word lines and the pad; and
a source selection line formed between the word lines and the common source line.

13. A semiconductor system, comprising:
a three-dimensional nonvolatile memory device comprising:
a plurality of word lines stacked over a substrate;
a first vertical hole and a second vertical hole vertically passing through the word lines;
a first vertical channel layer formed in the first vertical hole;
a second vertical channel layer formed in the second vertical hole, wherein the second vertical channel layer is coupled to the first vertical channel layer through a pipe channel layer;
tunnel insulating layers, charge trap layers and charge blocking layers surrounding the first vertical channel layer and the second vertical channel layer in each of the first vertical hole and the second vertical hole;
a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, wherein the pad and the contact plug are vertically in alignment with the first vertical channel layer, and a width of the pad is greater than that of the first vertical hole and that of the contact plug; and
a common source line formed over the second vertical channel layer; and

a memory controller configured to control at least one operation of the three-dimensional nonvolatile memory device.

Assignees

• Sk Hynix Inc

Inventors

• Kim Tae Kyung
• Eom Dae Sung

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H01L27/11578

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H10B43/00 Primary

  EEPROM devices comprising charge-trapping gate insulators · CPC title