Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
US9287201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9287201-B2 |
| Application number | US-201113988535-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 5, 2011 |
| Priority date | Dec 16, 2010 |
| Publication date | Mar 15, 2016 |
| Grant date | Mar 15, 2016 |
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Official abstract text for this publication.
A semiconductor device including: a semiconductor element; a lead frame connected to the semiconductor element; a metal base plate mounted on the lead frame via a first insulation layer; and a second insulation layer disposed on the opposite side of the metal base plate face on which the first insulation layer is disposed; wherein the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is the same as that of the first insulation layer or higher than that of the first insulation layer.
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device, comprising: a semiconductor element; a lead frame connected to the semiconductor element; a metal base plate mounted on the lead frame via a first insulation layer, a face of the metal base plate and the first insulation layer facing each other; a second insulation layer disposed on a side of the metal base plate face opposite the first insulation layer; and a cooling unit, directly connected to a side of the metal base plate, disposed on the second insulation layer on a side of the second insulation layer which faces the metal base plate, the side of the metal base plate being perpendicular to the face of the metal base plate. 2. A semiconductor device according to claim 1 , wherein the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is higher than that of the first insulation layer. 3. A semiconductor device according to claim 2 , wherein the first insulation layer and the second insulation layer include filler, and a filler particle size of the first insulation layer is greater than that of the second insulation layer. 4. A semiconductor device according to claim 2 , wherein the first insulation layer and the second insulation layer include filler, and a relative dielectric constant of filler of the first insulation layer is higher than that of filler of the second insulation layer. 5. A semiconductor device according to claim 2 , wherein a void fraction, which is a void content rate per unit volume, of the first insulation layer is higher than that of the second insulation layer. 6. A semiconductor device according to claim 2 , wherein the first insulation layer and the second insulation layer include filler, and a filling amount of filler of the first insulation layer is greater than that of filler of the second insulation layer. 7. A semiconductor device according to claim 2 , wherein a thickness of the first insulation layer is smaller than that of the second insulation layer. 8. A semiconductor device according to claim 1 , wherein the second insulation layer is formed by powder coating or electrodeposition coating. 9. A semiconductor device according to claim 1 , wherein the metal base plate is not connected to a ground-potential electrode that supplies a ground potential to the semiconductor element. 10. A semiconductor device according to claim 1 , wherein the semiconductor element includes wide-bandgap semiconductor material. 11. A semiconductor device according to claim 10 , wherein the wide-bandgap semiconductor material is any one of silicon carbide, gallium-nitride-based material and diamond. 12. A semiconductor device according to claim 1 , wherein: the first insulation layer is an insulation layer whose heat-dissipation performance is higher than that of the second insulation layer, and the second insulation layer is an insulation layer whose insulation performance is same as that of the first insulation layer or higher than that of the first insulation layer. 13. A semiconductor device according to claim 1 , wherein: the second insulation layer is an insulation layer whose insulation performance is higher than that of the first insulation layer, and the first insulation layer is an insulation layer whose heat-dissipation performance is same as that of the second insulation layer or higher than that of the second insulation layer. 14. A semiconductor device according to claim 1 , further comprising: a second cooling unit, connected to the metal base plate, disposed on the second insulation layer on the side of the second insulation layer which faces the metal base plate, the second cooling unit disposed on an opposite side of said semiconductor element as said cooling unit.
between laterally-adjacent chips · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
Package configurations · CPC title
by a substrate and the encapsulations · CPC title
changes in structures or sizes · CPC title
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