Power semiconductor module

Patent metadata

Field	Value
Publication number	US-9287187-B2
Application number	US-201214125019-A
Country	US
Kind code	B2
Filing date	Apr 16, 2012
Priority date	Jun 16, 2011
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A power semiconductor module has an insulating layer; a copper base substrate having first and second copper blocks, either the first or the second copper block being fixed on one side and the other being fixed on the other side of the insulating layer; a plurality of power semiconductor elements using silicon carbide, and having one side fixed onto the first copper block with a conductive bond layer; a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a conductive bond layer; a printed circuit board fixed to the implant pins and disposed to face the power semiconductor elements; a first sealing material containing no flame retardant, and disposed at least between the power semiconductor elements and the printed circuit board; and a second sealing material containing a flame retardant, and disposed to cover the first sealing material.

First claim

What is claimed is:

1. A semiconductor power module molded structure, comprising:
a case; and
a plurality of power semiconductor modules in the case, each of the power semiconductor modules comprising:
one insulating layer,
a copper base substrate having a first copper block and a second copper block, either the first or second copper block being fixed on one side of the one insulating layer and the other being fixed on the other side of the one insulating layer;
a plurality of power semiconductor elements having silicon carbide and formed on the copper base substrate, each having one side fixed onto the first copper block with a first conductive bond layer;
a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a second conductive bond layer;
a printed circuit board fixed to the plurality of implant pins and disposed to face the plurality of power semiconductor elements;
a first sealing material containing no flame retardant, and disposed only at a portion where the plurality of power semiconductor elements is enclosed, the first sealing material covering an upper portion and side portions of each of the plurality of power semiconductor elements between the copper base substrate and the printed circuit board;
a second sealing material containing a flame retardant, and disposed to cover the first sealing material; and
an external connection terminal extending upwardly from the copper base substrate to cross the printed circuit board,
wherein said plurality of power semiconductor elements is disposed on the one insulating layer with a space therebetween, only the first sealing material being disposed in the space and around said plurality of power semiconductor elements,
the second sealing material encloses an outer circumferential part of the first sealing material surrounding said plurality of power semiconductor elements to directly cover side portions of the first sealing material and indirectly cover an upper portion of the first sealing material through the printed circuit board,
the first sealing material contains no flame retardant to enhance a thermal resistant performance, and the second sealing material contains the flame retardant to resist oxidation degradation, and
the first sealing material encloses the external connection terminal between the copper base substrate and the printed circuit board,

wherein said plurality of power semiconductor modules is arranged side by side in the case,
the printed circuit boards of the plurality of power semiconductors are integrally connected to each other, and
the second sealing material is arranged in the case between the plurality of power semiconductor modules, and
wherein a heat distortion temperature of each of the first sealing materials is 175° C. to 225° C., a thermal expansion coefficient of each of the first sealing materials is 1.5×10 −5 /° C. to 1.8×10 −5 /° C., and a bonding strength of each of the first sealing materials to each of the copper base substrates is 10 MPa to 30 MPa; a heat distortion temperature of each of the second sealing materials is 100° C. to 175° C., a thermal expansion coefficient of each of the second sealing materials is 1.5×10 −5 /° C. to 1.8×10 −5 /° C., and a bonding strength of each of the second sealing materials to each of the copper base substrates is 10 MPa to 30 MPa; and liquid epoxy resin is used in the first sealing materials and the second sealing materials.

Assignees

• Yanagawa Katsuhiko
• Ikeda Yoshinari
• Fuji Electric Co Ltd

Inventors

• Yanagawa Katsuhiko
• Ikeda Yoshinari

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W76/15

  Containers comprising an insulating or insulated base · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W74/121 Primary

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title