Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9287181-B2
Application number	US-201514592842-A
Country	US
Kind code	B2
Filing date	Jan 8, 2015
Priority date	Mar 19, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device comprising:
forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench;
forming a high-k dielectric layer in the first trench;
successively forming a diffusion layer and a blocking layer on the high-k dielectric layer;
subsequently performing annealing;
after the annealing, successively removing the blocking layer and the diffusion layer;
forming a first barrier layer on the high-k layer;
successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and
forming a capping layer on the gate conductor.

2. The method of claim 1 , further comprising:
forming a second barrier layer on the work function adjustment layer prior to forming the gate conductor; and
forming a gate metal on the second barrier layer, thereby forming the gate conductor.

3. The method of claim 2 , wherein the forming the capping layer comprises removing a part of the gate metal, and forming the capping layer on a portion from which the part of the gate metal is removed, and
wherein the high-k dielectric layer and the second barrier layer are in a concave shape, and while the part of the gate metal is removed, a part of the high-k dielectric layer and a part of the second barrier layer are removed together.

4. The method of claim 1 , further comprising:
forming a second trench in the interlayer insulating layer;
forming the high-k dielectric layer in the second trench at the same time as forming the high-k dielectric layer in the first trench;
successively forming the diffusion layer and the blocking layer on the high-k dielectric layer in the second trench at the same time as successively forming the diffusion layer and the blocking layer on the high-k dielectric layer in the first trench;
successively removing the blocking layer and the diffusion layer from the second trench at the same time as successively removing the blocking layer and the diffusion layer from the first trench;
forming the first barrier layer on the high-k layer in the second trench at the same time as forming the first barrier layer on the high-k layer in the first trench;
successively forming a work function adjustment layer and a gate conductor on the first barrier layer in the second trench; and
forming a capping layer on the gate conductor in the second trench.

5. The method of claim 1 , wherein a thickness of the first barrier layer is between about 3 Å and about 30 Å.

6. The method of claim 1 , wherein the diffusion layer and the first barrier layer comprise different materials.

7. The method of claim 6 , wherein the diffusion layer comprises Ti, and the first barrier layer comprises Ta.

8. The method of claim 1 , wherein a thickness of the capping layer is between about 5 Å and about 500 Å.

9. The method of claim 8 , wherein the capping layer comprises an oxide layer or a nitride layer.

10. The method of claim 1 , wherein the performing the annealing comprises performing the annealing at a temperature between about 500° C. and 1500° C.

11. The method of claim 1 , wherein the capping layer covers the trench, and further comprising a spacer arranged on both sides of the first trench,
wherein side walls of the spacer contact side walls of the first trench.

12. The method of claim 1 , further comprising forming an interface layer on the substrate in the first trench before forming the high-k dielectric layer.

13. The method of claim 1 , further comprising forming a fin projecting from the substrate and extending in a first direction before forming the interlayer insulating layer,
wherein the first trench exposes an upper portion of the fin.

14. The method of claim 13 , further comprising forming a dummy gate structure before forming the interlayer insulating layer,
wherein the forming the interlayer insulating layer includes forming the interlayer insulating layer so that the interlayer insulating layer covers side walls of the dummy gate structure, and forming the first trench through removal of the dummy gate structure.

15. A method for fabricating a semiconductor device comprising:
forming an interlayer insulating layer on a substrate on which a first region and a second region are defined, the interlayer insulating layer including a first trench arranged in the first region and a second trench arranged in the second region;
forming a high-k dielectric layer in the first and second trenches;
successively forming a diffusion layer and a blocking layer on the high-k dielectric layer in the first and second trenches;
subsequently performing annealing;
after performing the annealing, removing the blocking layer in the first and second trenches;
forming a first barrier layer on the high-k dielectric layer in the first and second trenches;
forming a first work function adjustment layer in the second trench;
successively forming a second work function adjustment layer and a second barrier layer in the first and second trenches; and
forming a capping layer that covers the first and second trenches.

16. The method of claim 15 , further comprising forming a gate metal in the first trench so that the gate metal fills the first trench after forming the second barrier layer.

17. The method of claim 15 , further comprising removing the diffusion layer after removing the blocking layer,
wherein the first barrier layer comes in contact with the high-k dielectric layer.

18. The method of claim 15 , wherein the forming the first work function adjustment layer comprises forming the first work function adjustment layer on the first barrier layer in the first and second trenches, and removing the first work function adjustment layer in the first trench,
wherein the first barrier layer in the first trench is not removed while the first work function adjustment layer in the first trench is removed.

19. The method of claim 15 , wherein the performing the annealing comprises performing the annealing at a temperature between about 500° C. and about 1500° C.

20. The method of claim 15 , wherein the capping layer includes at least one of SiN, SiON, and SiCON.

21. The method of claim 15 , wherein the first region includes an NFET region, and the second region includes a PFET region.

22. A method for fabricating a semiconductor device comprising:
providing a substrate including a first region and a second region;
forming a first fin and a second fin that project from the first and second regions, respectively;
forming first and second dummy gate structures that cross the first and second fins, respectively;
forming first and second trenches that expose the first and second fins, respectively, through removal of the first and second dummy gate structures;
forming a high-k dielectric layer that crosses the fins in the first and second trenches;
successively stacking a diffusion layer and a blocking layer on the high-k dielectric layer and then performing annealing;
removing the blocking layer;
forming a first barrier layer in the first and second trenches;
forming a work function adjustment layer on the first barrier layer in the first and second trenches; and
forming first and second capping layers that cover the first and second trenches, respectively.

23. The method of claim 22 , further comprising removing the diffusion layer after removing the blocking layer.

24. The method of claim 22 , whe

Assignees

• Tseng Wei-Hsiung
• Kim Ju-Youn
• Won Seok-Jun
• Lee Jong-Ho
• Lee Hye-Lan
• Ha Yong-Ho
• Samsung Electronics Co Ltd

Inventors

• Tseng Wei-Hsiung
• Kim Ju-Youn
• Won Seok-Jun
• Lee Jong-Ho
• Lee Hye-Lan
• Ha Yong-Ho

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title