Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9287160-B2
Application number	US-201514826758-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Aug 21, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
patterning a substrate to form a plurality of first trenches defining a plurality of line patterns;
forming a plurality of device isolation patterns in the plurality of first trenches, each of the plurality of device isolation patterns including a first device isolation pattern and a second device isolation pattern;
patterning the plurality of line patterns and the plurality of device isolation patterns so as to form a plurality of second trenches extending across the plurality of first trenches and so as to define a plurality of active portions;
forming a plurality of gate patterns in the plurality of second trenches, each of the plurality of gate patterns including a gate insulating layer, a gate line and a gate capping pattern;
recessing at least one of the first device isolation pattern and the gate insulating layer so as to expose upper side surfaces of the plurality of active portions;
forming a metal layer covering the exposed upper side surfaces of the plurality of active portions; and
reacting the metal layer with the substrate to form a plurality of ohmic patterns on the plurality of active portions.

2. The method of claim 1 , wherein the first device isolation pattern is formed of silicon oxide, the gate insulating layer is formed of one selected from silicon oxide and metal oxides, the second device isolation pattern is formed of one selected from silicon nitride and silicon oxynitride, and the gate capping pattern is formed of one selected from silicon nitride and silicon oxynitride.

3. The method of claim 1 , further comprising:
performing a pre-treatment process so as to change a crystal structure of the plurality of active portions into an amorphous state, prior to the forming of the metal layer.

Assignees

• Nam Ki-Hyung
• Cho Pulunsol
• Kim Yong Kwan
• Samsung Electronics Co Ltd

Inventors

• Nam Ki-Hyung
• Cho Pulunsol
• Kim Yong Kwan

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D64/027

  by etching at gate locations · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title