Semiconductor memory device and system having redundancy cells

Patent metadata

Field	Value
Publication number	US-9287004-B2
Application number	US-201213670792-A
Country	US
Kind code	B2
Filing date	Nov 7, 2012
Priority date	Nov 7, 2011
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.

First claim

We claim:

1. A memory device, comprising:
a memory cell array having at least a first memory cell group, a second memory cell group, a first redundancy memory cell group and a second redundancy memory cell group, the first memory cell group including a plurality of first memory cells associated with a first data line, the second memory cell group including a plurality of second memory cells associated with a second data line, the first redundancy memory cell group including a plurality of redundancy memory cells associated with a first redundancy data line, and the second redundancy memory cell group including a plurality of redundancy memory cells associated with a second redundancy data line; and
a data line selection circuit configured to provide a data path between an input/output node and one of the first data line, the second data, the first redundancy data line, and the second redundancy data line, wherein
the data line selection circuit includes a first selection unit corresponding to a first memory cell group and a second selection unit corresponding to a second memory cell group,
the first redundancy data line is connected to the first selection unit and the second redundancy data line is connected to the second selection unit,
data from the first redundancy data line and the second redundancy data line are output through the first selection unit or the second selection unit according to a selected output data width, and
one or more of the first data line and the second data line are simultaneously replaced with the one or more of the first redundancy data line and the second redundancy data line, respectively, based on the selected output data width.

2. The memory device of claim 1 , further comprising:
selection control logic configured to control the data line selection circuit based on the selected output data width for the memory device.

3. The memory device of claim 2 , wherein the selection control logic is configured to control the data line selection circuit based on the selected output data width for the memory device and whether a defective memory cell in one of the first and second memory cell groups is detected.

4. The memory device of claim 1 , further comprising:
selection control logic configured to control the data line selection circuit based on whether a defective memory cell in one of the first and second memory cell groups is detected.

5. The memory device of claim 1 , wherein the data line selection circuit includes a multiplexer configured to provide the data path between the input/output node and one of the first data line, the second data line, the first redundancy data line and the second redundancy data line.

6. The memory device of claim 1 , wherein
the memory cell array includes first to nth memory cell groups, where n is greater than or equal to 2, each of the first to nth memory cell groups is associated with first to nth data lines, respectively; and
the data line selection circuit is configured to provide data paths between (i) the first redundancy data line, the second redundancy data line and the first to nth data lines and (ii) first to nth input/output nodes.

7. The memory device of claim 6 , wherein
the data line selection circuit includes first to nth selection units, each of the first to nth selection units is configured to selectively provide a data path between a connection node and one of a set of selection nodes, the connection node of each of the first to nth selection units being associated with a respective one of the first to nth input/output nodes;
the first selection unit having at least one selection node connected to the first redundancy data line and having at least another selection node connected to the first data line;
the second selection unit having one selection node connected to the second redundancy data line, and having at least another selection node connected to the first data line and having yet another selection node connected to the second data line; and
a ith selection unit having three selection nodes respectively connected to a (i−2)th data line-a the (i−1th) data line and the ith data line where i is 3 to n.

8. The memory device of claim 7 , further comprising:
selection control logic configured to control the data line selection circuit based on the selected output data width for the memory device and whether a defective memory cell in one of the first to nth memory cell groups is detected.

9. The memory device of claim 8 , wherein the selection control logic is configured to control the data line selection circuit to provide a data path between a ith memory cell group and the ith input/output node if the selected output data width is eight, wherein i is between 1 and 8.

10. The memory device of claim 9 , wherein the selection control logic is configured to replace access via one of the first to eighth data lines with access via the first redundancy data line and the second redundancy data line if a detected defective memory cell exists in the one of the first to eight memory cell groups.

11. The memory device of claim 10 , wherein
k is a whole number between 1 and n, and
if a kth memory cell group includes the detected defective memory cell, then the selection control logic is configured to control the data line selection circuit such that the first though kth input/output nodes are connected to the first redundancy data line, the second redundancy data line and the first through (k−1)th data lines, and the (k+1)th to the eighth input/output nodes are connected to the (k+1)th to eighth data lines.

12. The memory device of claim 10 , wherein if the kth memory cell group includes the detected defective memory cell, then the selection control logic is configured to control the data line selection circuit such that the first though (k−1)th input/output nodes are connected to the first through (k−1)th input/output nodes, and the kth to the eighth input/output nodes are connected the (k+1)th to eighth data lines, the first redundancy data line and the second redundancy data line.

13. The memory device of claim 9 , wherein
m is one of 1, 3, 5 and 7 in an odd operation mode and m is one of 2, 4, 6 and 8 in an even operation mode, and
the selection control logic controls the data lines selection circuit to provide a data path between a mth data line and a mth input/output node if the selected output data width is four.

14. The memory device of claim 13 , wherein the selection control logic is configured to replace access via one of the first, third, fifth and seventh data lines with access via the first redundancy data line and the second redundancy data line if a detected defective memory cell exists in the one of the first, third, fifth and seventh memory cell groups in the odd operation mode, and the selection control logic is configured to replace access via one of the second, fourth, sixth and eighth data lines with access via the first redundancy data line and the second redundancy data line if a detected defective memory cell exists in the one of the second, fourth, sixth and eighth memory cell groups in the even operation mode.

15. The memory device of claim 8 , wherein
i is between 1 and one of 16, 32 and 64, and
the selection control logic is configured to control the data line selection circuit to provide a data path between the ith memory cell group and the ith input/output node if the selected output data width is one of 16, 32 and 64.

16. The memory device of claim 15 , wherein
p is one of 16, 32 and 64, and
the selection control logic is configured to replace access via one of a first

Assignees

• Kim Su-A
• Sohn Young-Soo
• Kim Dae-Hyun
• Samsung Electronics Co Ltd

Inventors

• Kim Su-A
• Sohn Young-Soo
• Kim Dae-Hyun

Classifications

• G11C29/808

  using a flexible replacement scheme · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C29/848 Primary

  by adjacent switching · CPC title

• G11C29/81

  using a hierarchical redundancy scheme · CPC title