Partial block read voltage offset
US-2024071506-A1 · Feb 29, 2024 · US
US9286972B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9286972-B2 |
| Application number | US-201213402575-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 22, 2012 |
| Priority date | Feb 22, 2012 |
| Publication date | Mar 15, 2016 |
| Grant date | Mar 15, 2016 |
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An exemplary method for reading data stored in a flash memory. The method includes: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates an uncorrectable result; and performing the error correction operation according to the second set of LLR mapping values.
Opening claim text (preview).
What is claimed is: 1. A method for reading data stored in a flash memory, the method comprises: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a secon…
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