Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Patent metadata

Field	Value
Publication number	US-9286423-B2
Application number	US-201213435707-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

First claim

The invention claimed is:

1. A method of using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the FPGA being associated with a target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd, the method comprising:
in a defined cycle of time, applying a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state; and
said applying including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state; and wherein:
the device memory has a data width of Wd, and the target memory has a data width of Wt;
the input ports of the device memory include one or more read ports and one or more write ports;
Fd is less than or equal to (Ft)/((Wd/Wt))(At+Nd)), wherein:
Nd is set equal to the larger of the number of the read ports or the number of the write ports of the device memory, and
At is a given number representing a defined number of Ft clock cycles consumed to perform a read or a write operation of the target memory.

2. A method of using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the FPGA being associated with a target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd, the method comprising:
in a defined cycle of time, applying a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state; and
said applying including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state; and
wherein the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the method further comprising:
hiding a refresh of the target DRAM memory by
scrambling the addresses of the target DRAM memory to reduce the necessity for refreshing the target DRAM memory,
forcing a refresh in the target DRAM memory when a refresh of the DUT DRAM memory occurs, and
stopping a DUT clock while the refresh of the target memory is occurring, and restarting the DUT clock after the refresh of the target memory has finished.

3. A method of using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT), the DUT including a device memory having a number of input ports, the FPGA being associated with a target memory having a second number of input ports, said second number being less than said first number, the method comprising:
applying a given set of inputs to the device memory via the input ports of the device memory at a frequency Fd and in a defined cycle of time; and
applying said given set of inputs to the target memory via the input ports of the target memory at a frequency Ft, wherein Ft is greater than Fd, to apply all of said given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory,
wherein the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory, and the target DRAM memory is refreshed at determined times, and the method further comprising:
hiding the refresh of the target memory by hyper clocking the target memory so that the target memory and the DUT memory operate at different frequencies, and hiding the refresh of the target memory by using the frequency difference between the DUT memory operations and the target memory operations.

4. A system for simulating operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the system comprising:
at least one Field Programmable Gate Array (FPGA);
a target memory communicatively associated with the FPGA, the target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd;
a controller for applying in a defined cycle of time, a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
said applying including using said more target clock cycles of the target memory for multiplexing the given set of inputs to the target memory in said defined cycle of time to maintain cycle accuracy between the device memory and the target memory, wherein at the end of said defined cycle of time, the device memory and the target memory are in the same state; and wherein:
the DUT memory is a DUT DRAM memory and the target memory is a target DRAM memory; and
the target memory controller hides a refresh of the target DRAM memory by scrambling the addresses of the target DRAM memory to reduce the necessity for refreshing the target DRAM memory,
forcing a refresh in the target DRAM memory when a refresh of the DUT DRAM memory occurs, and
stopping a DUT clock while the refresh of the target memory is occurring, and restarting the DUT clock after the refresh of the target memory has finished.

5. A system for simulating operations of a device under test (DUT), the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the system comprising:
at least one Field Programmable Gate Array (FPGA);
a target memory communicatively associated with the FPGA, the target memory having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd;
a controller for applying in a defined cycle of time, a given set of inputs to the device memory via the input ports of the device memory and to the target memory via the input ports of the target memory, wherein in said defined cycle of time, the target memory has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memory has an associated state;
said applying

Assignees

• Asaad Sameh W
• Kapur Mohit
• IBM

Inventors

• Asaad Sameh W
• Kapur Mohit

Classifications

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G01R31/31703 Primary

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title