Method and apparatus for lowering I/O power of a computer system and computer system

Patent metadata

Field	Value
Publication number	US-9286259-B2
Application number	US-73890808-A
Country	US
Kind code	B2
Filing date	Oct 10, 2008
Priority date	Oct 22, 2007
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.

First claim

The invention claimed is:

1. A method for lowering I/O power of a computer system, comprising:
buffering a plurality of ways of data to be sent to a bus;
encoding each of said plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both integers larger than or equal to 1, and wherein said encoding rule is used to lower code switching frequency;
wherein said encoding rule comprises a code book mapping an n bit data space with an n+m bit data space, in which all codes of said n bit data space are mapped with codes of said n+m bit data space one by one; and
sending said plurality of ways of data encoded to said bus.

2. The method according to claim 1 , further comprising: monitoring a workload of said bus of said computer system before said encoding, and encoding each of said plurality of ways of data buffered when it is monitored that the workload of said bus is below a threshold.

3. The method according to claim 1 , further comprising: decoding said n+m bit data encoded into n bit data based on said encoding rule after receiving said n+m bit data encoded from said bus.

4. The method according to claim 3 , wherein said encoding and said decoding are implemented through hardware.

5. The method according to claim 3 , wherein said encoding and said decoding are implemented through software.

6. The method according to claim 2 , wherein said monitoring the workload of said bus comprises: obtaining the workload of said bus instantly when data are required to be transferred between a CPU and an I/O device.

7. The method according to claim 2 , further comprising: selecting a corresponding encoding rule based on said workload of said bus monitored.

8. The method according to claim 3 , wherein said each of said plurality of ways of data and said decoding are performed through respective encoders and decoders.

9. The method according to claim 3 , wherein said encoding and said decoding are performed through a shared encoder/decoder.

10. The method according to claim 1 , wherein switching times of each of all codes of said n bit data space is larger than or equal to switching times of a code of said n+m bit data space mapped with said code.

11. An apparatus for lowering I/O power of a computer system, comprising:
an original data buffer configured to buffer a plurality of ways of data to be sent to a bus;
an encoder configured to encode each of said plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both in larger than or equal to 1, and wherein said encoding rule is used to lower code switching frequency;
wherein said encoding rule comprises a code book mapping an n bit data space with an n+m bit data space, in which all codes of said n bit data space are mapped with codes of said n+m bit data space one by one; and
an encoded data buffer configured to buffer said plurality of ways of data encoded in order to send them to said bus.

12. The apparatus according to claim 11 , further comprising: a bus monitor configured to monitor a workload of said bus of said computer system, and each of said plurality of ways of data buffered are encoded by said encoder when it is monitored that the workload of said bus is below a threshold.

13. The apparatus according to claim 11 , further comprising: a decoder configured to decode said n+m bit data encoded into n bit data based on said encoding rule after receiving said n+m bit data encoded from said bus.

14. The apparatus according to claim 13 , wherein said encoder and said decoder are implemented through hardware.

15. The apparatus according to claim 13 , wherein said encoder and said decoder are implemented through software.

16. The apparatus according to claim 12 , wherein the workload of said bus is obtained instantly by said bus monitor when data are required to be transferred between a CPU and an I/O device.

17. The apparatus according to claim 12 , wherein a corresponding encoding rule is selected by said bus monitor based on said workload of said bus monitored.

18. The apparatus according to claim 13 , wherein said encoder comprises a plurality of encoders/decoders configured to encode and decode each of said plurality of ways of data respectively.

19. The apparatus according to claim 13 , wherein said encoder and said decoder are shared by said plurality of ways of data.

20. The apparatus according to claim 11 , wherein switching times of each of all codes of said n bit data space is larger than or equal to switching times of a code of said n+m bit data space mapped with said code.

21. The apparatus according to claim 11 , wherein said original data buffer and said encoded data buffer are implemented through a shift register and a shift counter.

22. A computer system, comprising:
a CPU;
an I/O device;
a bus configured to transfer data between said CPU and said I/O device;
an original data buffer configured to buffer a plurality of ways of data to be sent to the bus;
an encoder configured to encode each of said plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both integers larger than or equal to 1, and wherein said encoding rule is used to lower code switching frequency;
wherein said encoding rule comprises a code book mapping an n bit data space with an n+m bit data space, in which all codes of said n bit data space are mapped with codes of said n+m bit data space one by one; and
an encoded data buffer configured to buffer said plurality of ways of data encoded in order to send them to said bus.

Assignees

• Li Yu
• Shen Wen Bo
• Wang Yan Qi
• Yang Yudong
• IBM

Inventors

• Li Yu
• Shen Wen Bo
• Wang Yan Qi
• Yang Yudong

Classifications

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/4286 Primary

  using a handshaking protocol, e.g. RS232C link · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F13/14

  Handling requests for interconnection or transfer · CPC title