Virtual memory address range register

Patent metadata

Field	Value
Publication number	US-9286235-B2
Application number	US-201213538900-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jun 29, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

First claim

What is claimed is:

1. A processor comprising:
a memory interface to access a system memory using a physical memory address;
address translation hardware to support translation of a virtual memory address to the physical memory address, the virtual memory address used by software to access a virtual memory location in a virtual memory address space of the processor;
a virtual memory address range register programmable by user level software to store a virtual memory base address of a virtual memory address range; and
virtual memory address comparison hardware to determine whether the virtual memory address is within the virtual memory address range.

2. The processor of claim 1 , further comprising a physical memory address range register to store a physical memory base address of a physical memory address range.

3. The processor of claim 2 , further comprising physical memory address comparison hardware to determine whether the physical memory address is within the physical memory address range.

4. The processor of claim 3 , further comprising a mask register to store a mask value.

5. The processor of claim 4 , further comprising a first AND circuit to generate a current virtual memory address range value based on the virtual memory address and the mask value.

6. The processor of claim 5 , further comprising a second AND circuit to generate a programmed virtual memory address range value based on the virtual memory base address and the mask value.

7. The processor of claim 6 , wherein the virtual memory address comparison hardware determines whether the virtual memory address is within the virtual memory address range by comparing the current virtual memory address range value to the programmed virtual memory address range value.

8. The processor of claim 7 , further comprising a latch to store a match signal, the match signal indicating that the current virtual memory address range value matches the programmed virtual memory address range value.

9. A method comprising:
programming, by user level software, a virtual memory address range register with a virtual memory base address of a virtual memory address range; and
determining whether a virtual memory address is within the virtual memory address range.

10. The method of claim 9 , further comprising programming a mask register with a mask value.

11. The method of claim 10 , further comprising generating a current virtual memory address range value based on the virtual memory address and the mask value.

12. The method of claim 11 , further comprising generating a programmed virtual memory address range value based on the virtual memory base address and the mask value.

13. The method of claim 12 , wherein the virtual memory address comparison hardware determines whether the virtual memory address is within the virtual memory address range by comparing the current virtual memory address range value to the programmed virtual memory address range value.

14. The method of claim 13 , wherein determining that the virtual memory address is within the virtual memory address range invokes a security checking action.

15. A system comprising:
a system memory; and
a processor including
an interface to access the system memory using a physical memory address;
address translation hardware to support translation of a virtual memory address to the physical memory address, the virtual memory address used by software to access a virtual memory location in a virtual memory address space of the processor;
a virtual memory address range register programmable by user level software to store a virtual memory base address of a virtual memory address range; and
virtual memory address comparison hardware to determine whether the virtual memory address is within the virtual memory address range.

16. The system of claim 15 , further comprising a physical memory address range register to store a physical memory base address of a physical memory address range.

17. The system of claim 16 , further comprising physical memory address comparison hardware to determine whether the physical memory address is within the physical memory address range.

Assignees

• Hildesheim Gur
• Raikin Shlomo
• Anati Ittai
• Gerzon Gideon
• Savagaonkar Uday
• Mckeen Francis
• Rozas Carlos
• Goldsmith Michael
• Dewan Prashant
• Intel Corp

Inventors

• Hildesheim Gur
• Raikin Shlomo
• Anati Ittai
• Gerzon Gideon
• Savagaonkar Uday
• Mckeen Francis
• Rozas Carlos
• Goldsmith Michael
• Dewan Prashant

Classifications

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F12/0284

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/656

  Address space sharing · CPC title