Oldest operation translation look-aside buffer

Patent metadata

Field	Value
Publication number	US-9286233-B2
Application number	US-201213599269-A
Country	US
Kind code	B2
Filing date	Aug 30, 2012
Priority date	Aug 30, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.

First claim

The invention claimed is:

1. A method, comprising:
dispatching an operation to a processing device;
in response to determining that the operation is the oldest load operation:
storing a translation for the operation in a buffer configured to hold only the translation for the oldest load operation in a processing system; and
executing the operation using the translation.

2. The method of claim 1 , further comprising:
generating an address for the operation subsequent to the dispatching of the operation to a load-store unit.

3. The method of claim 2 , further comprising:
transmitting the address to a translation look-aside buffer (TLB); and
determining whether the TLB returns an address hit or an address miss.

4. The method of claim 3 , further comprising:
performing a page translation in response to determining an address miss.

5. The method of claim 4 , wherein performing the page translation comprises performing a tablewalk.

6. The method of claim 4 , further comprising:
performing one or more actions until an address hit is returned by the TLB, the one or more actions comprising:
determining whether the TLB returns an address hit or an address miss in response to performing the page translation; and
performing a subsequent page translation in response to determining the most recent address miss.

7. The method of claim 3 , further comprising:
performing, in response to determining an address hit, at least one of:
determining that the operation is cacheable or non-cacheable;
transmitting the address to the TLB in response to determining the operation is cacheable or non-cacheable and is the oldest load operation; and
determining whether the TLB returns an address hit or an address miss for the oldest load operation.

8. The method of claim 7 , further comprising:
performing a page translation in response to determining the address miss for the oldest load operation.

9. The method of claim 7 , wherein:
storing the translation in the buffer is performed further in response to the address hit for the oldest load operation.

10. The method of claim 9 , further comprising:
accessing the translation for the oldest load operation from the buffer; and
wherein executing the oldest load operation comprising executing the selected oldest load operation using the translation accessed from the buffer.

11. The method of claim 1 , wherein the operation is at least one of a speculative operation or a non-cacheable operation.

12. The method of claim 1 , wherein the operation is misaligned with respect to at least one of a cache line or a page.

13. The method of claim 12 , wherein each portion of the misaligned operation has a respective, valid memory translation.

14. The method of claim 13 , further comprising:
storing each portion of the translation for a misaligned operation in the buffer, wherein storing each portion of the translation for the misaligned operation in the buffer is performed in response to an address hit for each portion of the misaligned operation in the buffer is performed in response to an address hit for each portion of the misaligned operation.

15. The method of claim 14 , wherein storing the translation for each portion of the misaligned operation comprises at least one of:
processing and storing each portion of the translation for the misaligned operation independently of each other;
processing and storing each portion of the translation for the misaligned operation sequentially; or
processing and storing each portion of the translation for the misaligned operation in parallel.

16. A non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform a method, the method comprising:
dispatching an operation to the processing device;
in response to determining that the operation is the oldest load operation:
storing a translation for the operation in a buffer configured to hold only the translation for the oldest load operation in a processing system; and
executing the operation using the translation.

17. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 16 , further comprising:
generating an address for the operation subsequent to the dispatching of the operation to a load-store unit.

18. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 17 , further comprising:
transmitting the address to a translation look-aside buffer (TLB);
determining whether the TLB returns an address hit or an address miss; and
performing a page translation in response to determining an address miss.

19. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 18 , wherein performing the page translation comprises performing a tablewalk, and further comprising:
performing one or more actions until an address hit is returned by the TLB, the one or more actions comprising:
determining whether the TLB returns an address hit or an address miss in response to performing the page translation; and
performing a subsequent page translation in response to determining the most recent address miss.

20. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 18 , further comprising:
performing, in response to determining an address hit, at least one of:
determining that the operation is cacheable or non-cacheable;
transmitting the address to a translation look-aside buffer (TLB) in response to determining the operation is cacheable or non-cacheable and is the oldest load operation; and
determining whether the TLB returns an address hit or an address miss for the oldest load operation.

21. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 20 , further comprising at least one of:
performing a page translation in response to determining the address miss for the oldest load operation; and
wherein storing the translation for the oldest load operation in the buffer is performed further in response to the address hit for the oldest load operation.

22. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 21 , further comprising:
accessing the translation for the oldest load operation from the buffer; and
wherein executing the selected oldest load operation comprises executing the selected oldest load operation using the accessed translation.

23. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the method as in claim 16 , wherein the operation is at least one of a speculative operation or a non-cacheable operation.

24. The non-transitory, computer-readable storage device encoded with data that, when executed by a processing device, adapts the processing device to perform the

Assignees

• Kaplan David
• King John M
• Advanced Micro Devices Inc

Inventors

• Kaplan David
• King John M

Classifications

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title