Method and system for compiler identification of code for parallel execution

Patent metadata

Field	Value
Publication number	US-9286090-B2
Application number	US-201414382886-A
Country	US
Kind code	B2
Filing date	Jan 20, 2014
Priority date	Jan 20, 2014
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A method in a system for handling compiled code is provided. The system comprises a Just-In-Time, JIT, compiler for compiling code, and at least one array processor unit comprising a plurality of processors for executing program code. The method comprises compiling input program code, whereby compiled program code is generated for the input program code. While compiling at least two parts of the compiled program code to be executed in parallel are identified. The identified at least two parts of compiled code are executed in parallel speculatively on at least two respective of the plurality of processors. Control if the at least two parts of in parallel executed code are in conflict with each other is performed, and if the parts are in conflict, the parts are executed again.

First claim

The invention claimed is:

1. A method executed in a system for handling compiled program code comprising:
a Just-In-Time, JIT, compiler for compiling input program code, wherein the JIT compiler is adapted to identify compiled program code to be executed in parallel, and
at least one array processor unit comprising a plurality of processors for executing the compiled program code, the method comprising:
compiling the input program code by the JIT compiler, whereby the compiled program code is generated from the input program code;
while compiling the input program code by the JIT compiler, identifying, by the JIT compiler, at least two parts of the compiled program code to be executed in parallel;
mapping the identified at least two parts of the compiled program code to be executed speculatively in parallel on at least two respective ones of the plurality of processors;
determining that the identified at least two parts of the compiled program code being executed speculatively in parallel are in conflict with each other; and
responsive to determining that the identified at least two parts of the compiled program code being executed speculatively in parallel are in conflict with each other, repeating the mapping and the determining.

2. The method according to claim 1 , further comprising that the identified at least two parts of the compiled program code comprises a same number of instructions.

3. The method according to claim 1 , further comprising that more than two parts of the compiled program code are identified.

4. The method according to claim 1 , further comprising that at least one of the identified at least two parts of the compiled program code comprises two or more functions merged together into a single function.

5. The method according to claim 4 , further comprising that more than two functions are merged together into a single function.

6. The method according to claim 4 , further comprising that the two or more functions comprise a same number of instructions.

7. The method according to claim 1 , further comprising that all of the identified at least two parts of the compiled program code comprises two or more functions merged together into a single function.

8. The method according to claim 1 , further comprising, in the compiling, identifying parts of the compiled program code being frequently executed, and performing the identifying of the at least two parts of the compiled program code to be executed in parallel, the mapping, and the determining for the frequently executed parts of the compiled program code.

9. The method according to claim 1 , further comprising, in the mapping, identifying parts of the compiled program code being frequently executed, and performing the identifying of the at least two parts of the compiled program code to be executed in parallel, the mapping, and the determining for the frequently executed parts of the compiled program code.

10. The method according to claim 1 , wherein the at least one array processor unit comprises one or more General Purpose Graphics Processing Units, GPGPUs, and wherein the parallel execution of the compiled program code is performed on a plurality of processors comprised in the GPGPUs.

11. The method according to claim 10 , wherein the GPGPUs are combined with a Central Processing Unit, CPU.

12. The method according to claim 1 , wherein statistics of the compiled program code are gathered during the parallel execution of the compiled program code.

13. The method according to claim 1 , wherein the input program code is JavaScript code.

14. The method according to claim 1 , wherein the identified at least two parts of the compiled program code are functions.

15. The method according to claim 1 , wherein more than two parts of the compiled program code are identified and executed in parallel.

16. The method according to claim 15 , wherein the more than two parts of the compiled program code are a plurality of functions.

17. A system for handling compiled program code comprising:
a Just-In-Time, JIT, compiler for compiling input program code, wherein the JIT compiler is adapted to identify compiled program code to be executed in parallel; and
at least one array processor unit comprising a plurality of processors for executing the compiled program code,
wherein the JIT compiler is adapted to compile the input program code, whereby the compiled program code is generated from the input program code, and is further adapted to, while compiling the input program code, identify at least two parts of the compiled program code to be executed in parallel,
wherein the at least one array processor unit is adapted to map the identified at least two parts of the compiled program code to be executed speculatively in parallel on at least two respective ones of the plurality of processors, and is further adapted to determine that the identified at least two parts of the compiled program code being executed speculatively in parallel are in conflict with each other, and
wherein the system is adapted to, responsive to determining that if the identified at least two parts of the compiled program code being executed speculatively in parallel are in conflict with each other, repeat the mapping and the determining.

18. The system according to claim 17 , wherein the at least one array processor unit comprises one or more General Purpose Graphics Processing Units, GPGPUs, and wherein the parallel execution of the compiled program code is performed on a plurality of processors comprised in the GPGPUs.

Assignees

• Sony Corp

Inventors

• Isberg Anders
• Gustavsson Jonas
• Rasmusson Jim

Classifications

• G06F8/4452 Primary

  Software pipelining · CPC title

• G06F9/4552 Primary

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

• G06F8/456

  Parallelism detection · CPC title