Systems and methods for DQS gating

Patent metadata

Field	Value
Publication number	US-9285824-B2
Application number	US-201313873658-A
Country	US
Kind code	B2
Filing date	Apr 30, 2013
Priority date	May 1, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a falling edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal.

First claim

It is claimed:

1. A system for timing read operations in which a memory controller sends a read request to a memory device and receives, from the memory device, data and a timing signal, and in which the timing signal includes a series of timing pulses that include a first timing pulse and a last timing pulse, the system comprising:
a timing control circuit configured to, in response to the read request, generate a control signal pulse that has (i) a leading edge at a predetermined delay past receipt of the read request and (ii) a trailing edge at a trailing edge of the first timing pulse;
a gating circuit configured to pass the timing signal to the memory controller only during a gating window and to generate the gating window by:
opening the gating window during the control signal pulse, and
closing the gating window upon lapse of a predetermined delay after a trailing edge of the last timing pulse, the last timing pulse being determined based on a counter that is triggered to begin counting by the control signal pulse.

2. The system of claim 1 , wherein the gating circuit includes:
the counter;
a first module configured to generate a first intermediate signal pulse that has (i) a leading edge that is triggered during the control signal pulse by a leading edge of the first timing pulse, and (ii) a trailing edge that is triggered by a leading edge of the last timing pulse; and
a second module configured to generate a second intermediate signal pulse that has (i) a leading edge triggered by a trailing edge of the first timing pulse during the first intermediate signal pulse and (ii) a trailing edge triggered by a trailing edge of the last timing pulse;
wherein the generating of the gating window pulse is by ORing together the control signal pulse, the first intermediate signal pulse, and the second intermediate signal pulse.

3. The system of claim 1 , wherein the gating window is configured to close after a delay following the trailing edge of the last timing pulse, and wherein the gating window closes during a postamble portion of the timing signal.

4. The system of claim 3 , wherein the delay is caused by a D flip-flop and an “OR” logic gate.

5. The system of claim 1 , wherein the and circuit delays generation of the control signal pulse to cause the leading edge of the control signal pulse to be at or near a center of a preamble portion of the timing signal, and wherein the delayed generation is based on a calibration process.

6. The system of claim 5 , wherein the calibration process includes an initial calibration to determine an initial delay setting for generating the control signal pulse, and wherein the calibration process includes a runtime calibration to adjust the initial delay setting based on voltage or temperature changes in the memory device or the memory controller.

7. The system of claim 5 , further comprising:
a monitor circuit configured to determine a relationship between the timing signal and the control signal pulse, wherein the monitor circuit includes:
a first module triggered to a second trailing edge of the timing signal, the first module being configured to read the control signal pulse contemporaneously with the second trailing edge and generate a first output signal for the calibration process,
a second module triggered to a leading edge of the timing signal, the second module being configured to read the control signal pulse contemporaneously with the leading edge and generate a second output signal for the calibration process, and
a third module triggered to a second leading edge of the timing signal, the third module being configured to read the control signal pulse and a count signal from the counter contemporaneously with the second leading edge and generate a third output signal for the calibration process.

8. The system of claim 5 , wherein the calibration process includes a low power mode during which calibration procedures are suspended, and wherein upon exiting the low power mode, a delay setting for the control signal pulse is left unchanged or reset to an initial value.

9. The system of claim 1 , wherein the gating circuit is configured to process a burst chop signal, wherein the burst chop signal includes a pulse that is four cycles in duration, and wherein the burst chop signal indicates that a current command is a burst chop command.

10. The system of claim 1 , wherein the delayed generation of the control signal pulse is based on a first input defining a number of clock cycles to delay, a second input defining a delay based on a leading edge or a trailing edge of the timing pulse, and a third input defining a delay based on a delay line.

11. The system of claim 1 , wherein a width of a pulse of the control signal pulse is equal in duration to a width of the preamble portion of the timing signal.

12. The system of claim 1 , wherein the gating window is closed automatically, and wherein a second control signal pulse is not generated to close the gating window.

13. The system of claim 1 , wherein the gating circuit includes logic configured to process a read interrupt command, the read interrupt command being a second read request that is received prior to completing processing of a first read request.

14. A method for timing read operations in which a memory controller sends a read request to a memory device and receives, from the memory device, data and a timing signal, and in which the timing signal includes a series of timing pulses including a first timing pulse and a last timing pulse, the method comprising:
generating, in response to the read request, a control signal pulse that has (i) a leading edge at a predetermined delay past receipt of the read request and (ii) a trailing edge at a trailing edge of the first timing pulse;
passing the timing signal to the memory controller only during a gating window; and
generating the gating window by:
opening the gating window during the control signal pulse, and
closing the gating window upon lapse of a predetermined delay after a trailing edge of the last timing pulse, the last timing pulse being determined based on a counter that is triggered to begin counting by the control signal pulse.

15. The method of claim 14 , further comprising:
generating a first intermediate signal pulse that has (i) a leading edge that is triggered during the control signal pulse by a leading edge of the first timing pulse, and (ii) a trailing edge that is triggered by a leading edge of the last timing pulse;
generating a second intermediate signal pulse that has (i) a leading edge triggered by a trailing edge of the first timing pulse during the first intermediate signal pulse and (ii) a trailing edge triggered by a trailing edge of the last timing pulse;
wherein the generating of the gating signal is by ORing together the control signal pulse, the first intermediate signal, and the second intermediate signal.

16. The method of claim 14 , wherein the gating window is configured to close after a delay following a trailing edge of the last timing pulse, and wherein the gating window closes during a postamble portion of the timing signal.

17. The method of claim 16 , wherein the delay is caused by a D flip-flop and an “OR” logic gate.

18. The method of claim 14 , wherein the generation of the control signal pulse is delayed to cause a leading edge of the control signal pulse to be at or near a center of a preamble portion of the timing signal, and wherein the delayed generation is based on a calibration process.

19. The method of claim 18 , further

Assignees

• Marvell World Trade Ltd

Inventors

• Zhu Jun
• Cao Joseph Jun
• Lu Sheng

Classifications

• G06F13/4243

  with synchronous protocol · CPC title

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title