Clock and data recovery with high jitter tolerance and fast phase locking

Patent metadata

Field	Value
Publication number	US-9281934-B2
Application number	US-201414268850-A
Country	US
Kind code	B2
Filing date	May 2, 2014
Priority date	May 2, 2014
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

First claim

What is claimed is:

1. A circuit for recovering clock and data from a serial data input signal using clock phase signals, the data input signal containing a serial stream of data, the clock phase signals oscillating at a frequency that approximately matches a data rate of the data input signal, and the clock phase signals equally spaced in phase, the circuit comprising:
a phase sampler configured to sample values of clock phase signals on edges of a data input signal;
a phase adjuster configured to evaluate the sampled values of the clock phase signals to determine the last of the clock phase signals to rise before a respective edge of the data input signal and determine a timing relationship between the data input signal and the clock phase signals utilizing the last of the clock phase signals to rise before the respective edge of the data input signal;
a phase selector configured to produce a clock output signal using the clock phase signals based on the timing relationship between the data input signal and the clock phase signals determined by the phase adjuster; and
a data sampler configured to produce a data output signal by sampling the data input signal on edges of the clock output signal.

2. The circuit of claim 1 , wherein the phase selector is further configured to produce the clock output signal to have a leading edge with a predetermined offset from the last of the clock phase signals to rise before the respective edge of the data input signal.

3. The circuit of claim 2 , wherein the predetermined offset equals one-half of a period of the clock phase signals.

4. The circuit of claim 1 , further comprising a glitch suppression module configured to suppress glitches on the clock output signal.

5. The circuit of claim 4 , wherein the glitch suppression module suppresses the clock output signal for a time interval after edges of the data input signal.

6. The circuit of claim 1 , wherein the number of clock phase signals is eight.

7. The circuit of claim 6 , wherein the clock output signal has a duty cycle of ⅜ of a period of the clock phase signals.

8. The circuit of claim 1 , wherein the phase sampler is configured to sample the values of the clock phase signals on rising and falling edges of the data input signal.

9. The circuit of claim 1 , further comprising a pulse generator module configured to generate a sample pulse signal on edges of the data input signal, and wherein the phase sampler is configured to sample the values of the clock phase signals triggered by the sample pulse signal.

10. The circuit of claim 9 , wherein the pulse generator module is further configured to generate a glitch suppression pulse signal, and the clock and data recovery circuit further comprises a glitch suppression module configured to suppress glitches on the clock output signal using the glitch suppression pulse signal.

11. A method for recovering clock and data from a data input signal, the method comprising:
sampling values of clock phase signals on edges of the data input signal;
evaluating the sampled values of the clock phase signals to determine the last of the clock phase signals to rise before a respective edge of the data input signal;
determining a timing relationship between the data input signal and the clock phase signals utilizing the last of the clock phase signals to rise before the respective edge of the data input signal;
producing a clock output signal using the clock phase signals based on the determined timing relationship between the data input signal and the clock phase signals; and
sampling the data input signal on edges of the clock output signal to produce a data output signal.

12. The method of claim 11 , wherein producing the clock output signal comprises producing the clock output signal to have a leading edge with a predetermined offset from the last of the clock phase signals to rise before the respective edge of the data input signal.

13. The method of claim 12 , wherein the predetermined offset equals one-half of a period of the clock phase signals.

14. The method of claim 11 , further comprising suppressing glitches on the clock output signal.

15. The method of claim 14 , wherein suppressing glitches comprises suppressing the clock output signal for a time interval after edges of the data input signal.

16. The method of claim 11 , wherein the values of the clock phase signals are sampled on rising and falling edges of the data input signal.

17. The method of claim 11 , further comprising generating a sample pulse signal on edges of the data input signal, and wherein sampling the values of the clock phase signals uses the sample pulse signal.

18. The method of claim 17 , further comprising:
generating a glitch suppression pulse signal; and
suppressing glitches on the clock output signal using the glitch suppression pulse signal.

19. An apparatus for recovering clock and data from a data input signal, the apparatus including:
a means for sampling values of clock phase signals on edges of the data input signal;
a means for evaluating the sampled values of the clock phase signals to determine the last of the clock phase signals to rise before a respective edge of the data input signal and determine a timing relationship between the data input signal and the clock phase signals utilizing the last of the clock phase signals to rise before the respective edge of the data input signal;
a means for producing a clock output signal using the clock phase signals based on the determined timing relationship between the data input signal and the clock phase signals; and
a means for sampling the data input signal on edges of the clock output signal to produce a data output signal.

20. The apparatus of claim 19 , wherein the means for producing the clock output signal is produces the clock output signal to have a leading edge with a predetermined offset from the last of the clock phase signals to rise before the respective edge of the data input signal.

21. The apparatus of claim 20 , wherein the predetermined offset equals one-half of a period of the clock phase signals.

22. The apparatus of claim 19 , further comprising a means for suppressing glitches on the clock output signal.

23. The apparatus of claim 22 , wherein the means for suppressing glitches suppresses the clock output signal for a time interval after edges of the data input signal.

24. The apparatus of claim 19 , wherein the means for sampling samples the values of the clock phase signals on rising and falling edges of the data input signal.

25. The apparatus of claim 19 , further comprising a pulse generator module configured to generate a sample pulse signal on edges of the data input signal, and wherein the means for sampling samples the values of the clock phase signals triggered by the sample pulse signal.

26. The apparatus of claim 25 , wherein the pulse generator module is further configured to generate a glitch suppression pulse signal, and the apparatus further comprises a means for suppressing glitches on the clock output signal using the glitch suppression pulse signal.

Assignees

• Qualcomm Inc

Inventors

• Song Yu
• Diffenderfer Jan Christian
• Chen Nan
• West David Ian
• Viani Paul Lawrence

Classifications

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H04L7/0338

  the correction of the phase error being performed by a feed forward loop · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L7/0083

  taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks · CPC title