Interface circuit, and semiconductor device and liquid crystal display device including the same

Patent metadata

Field	Value
Publication number	US-9281818-B2
Application number	US-97278010-A
Country	US
Kind code	B2
Filing date	Dec 20, 2010
Priority date	Dec 30, 2009
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A method of reducing power consumption caused by leakage current in an interface circuit between modules that are driven by different power sources is disclosed. The interface circuit includes an output driver that operates by a first power supply voltage in a first mode and does not operate in a second mode in which the first power supply voltage is prevented from being applied, an input buffer that is operated by a second power supply voltage in the first and second modes, and a transmission line that connects an output terminal of the output driver to an input terminal of the input buffer. The interface circuit further includes a current leakage prevention circuit that prevents, in the second mode, a current leakage in the input buffer between a second power supply voltage source that supplies the second power supply voltage and a ground voltage source.

First claim

What is claimed is:

1. A liquid crystal display system comprising:
a liquid crystal display panel in which a plurality of scan lines and a plurality of data lines intersect one another crosswise, where a switching unit and a pixel electrode are disposed at each of the intersections;
a memory including at least one output driver being driven by a first power supply voltage in a first mode, for outputting image data stored in a cell via the at least one output driver, wherein the memory is configured to store data in the first mode and does not store data in a second mode;
a driving unit including at least one input buffer being driven by a second power supply voltage, the driving unit configured to receive data stored in the memory via the at least one input buffer, generate at least one gray-scale voltage signal corresponding to the received data, and sequentially supply the at least one gray-scale voltage signal to a respective at least one data line of the data lines of the liquid crystal panel; and
a power source that provides the first power supply voltage to the memory and the second power supply voltage to the driving unit in the first mode and does not provide the first power supply voltage to the memory in the second mode,
wherein the input buffer includes a circuit configured to prevent a current path from being formed between the second power supply voltage source and a ground voltage source in the second mode, and
wherein an output terminal of the at least one output driver is connected to an input terminal of the at least one input buffer via a transmission line.

2. The liquid crystal display system of claim 1 , wherein the at least one input buffer comprises:
a blocking unit that comprises the circuit, the blocking unit configured to block a current path between the second power supply voltage source and the ground voltage source regardless of a level of the voltage at the input terminal of the input buffer, according to a first control signal; and
an inverter for inverting and outputting an output of the blocking unit.

3. The liquid crystal display system of claim 2 , wherein the blocking unit comprises one of a NAND gate or a NOR gate to which a signal from the input terminal and the first control signal are supplied.

4. The liquid crystal display system of claim 3 , wherein the input buffer further comprises:
a first diode, a cathode and anode of which are connected to the second power supply voltage source and the input terminal, respectively, the first diode for providing a static electricity discharge path for the second power supply voltage source; and
a second diode, a cathode and anode of which are connected to the input terminal and the ground voltage source, respectively, the second diode for providing a static electricity discharge path for the ground voltage source.

5. The liquid crystal display system of claim 1 , wherein the output driver is configured such that the first power supply voltage is applied in the first mode and is prevented from being applied in the second mode in response to a second control signal, the second control signal having a first logic level in the first mode and a second logic level opposite to the first logic level in the second mode.

6. The liquid crystal display system of claim 5 , wherein, if the first mode is switched to the second mode, the first control signal transitions before the second control signal transitions, and
wherein, if the second mode is switched to the first mode, the second control signal transitions before the first control signal transitions.

7. The liquid crystal display system of claim 1 , wherein after the current path is prevented in response to a first control signal, the first power supply voltage is prevented from being applied to the output driver.

Assignees

• Lim Sang-Hoon
• Lee Ji-Hyun
• Lee Jae-Youn
• Samsung Electronics Co Ltd

Inventors

• Lim Sang-Hoon
• Lee Ji-Hyun
• Lee Jae-Youn

Classifications

• G09G2330/027

  Arrangements or methods related to powering off a display · CPC title

• G09G2330/022

  in absence of operation, e.g. no data being entered during a predetermined time · CPC title

• G09G2330/04

  Display protection · CPC title

• G09G3/3611

  Control of matrices with row and column drivers · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title