Amplifier circuit

Patent metadata

Field	Value
Publication number	US-9281790-B2
Application number	US-201514599639-A
Country	US
Kind code	B2
Filing date	Jan 19, 2015
Priority date	Feb 20, 2014
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

An amplifier circuit has a plurality of amplifiers configured to be connected in series, and each of the plurality of amplifiers has an amplifying element configured to non-inverting amplify a signal and a phase adjustment element configured to be connected to an output terminal of the amplifying element and to adjust a phase of the signal, wherein the amplifying element is subjected to negative feedback, and wherein a stability coefficient of a circuit in which the amplifying elements of the number the same as the number of the plurality of amplifiers are connected in series is less than 1.

First claim

What is claimed is:

1. An amplifier circuit comprising
a plurality of amplifiers configured to be connected in series, each of the plurality of amplifiers comprising:
an amplifying element configured to non-inverting amplify a signal; and
a phase adjustment element configured to be connected to an output terminal of the amplifying element and to adjust a phase of the signal,

wherein the amplifying element is subjected to negative feedback, and
wherein a stability coefficient of a circuit in which the amplifying elements of the number the same as the number of the plurality of amplifiers are connected in series is less than 1.

2. The amplifier circuit according to claim 1 ,
wherein the amplifying element has a grounded-gate filed effect transistor or a grounded-base bipolar transistor.

3. The amplifier circuit according to claim 1 ,
wherein the amplifying element has a field effect transistor whose gate terminal is grounded in an AC manner and whose source terminal and drain terminal are an input terminal and an output terminal respectively.

4. The amplifier circuit according to claim 3 ,
wherein the amplifying element has a parasitic capacitance connected between the gate terminal and the drain terminal of the field effect transistor.

5. The amplifier circuit according to claim 4 ,
wherein an output signal of the drain terminal of the field effect transistor is reflected after passing through the phase adjustment element, and
wherein the reflected signal is inputted to the gate terminal of the field effect transistor via the phase adjustment element and the parasitic capacitance.

6. The amplifier circuit according to claim 1 ,
wherein the phase adjustment element has a line or a capacitance to delay a signal.

7. The amplifier circuit according to claim 1 ,
wherein the phase adjustment element has a plurality of lines with different phase shift amounts to delay a signal, and a switch element which connects the output terminal of the amplifying element to any one of the plurality of lines.

8. The amplifier circuit according to claim 1 ,
wherein the phase adjustment element has a varactor diode.

9. The amplifier circuit according to claim 1 ,
wherein an S parameter S 22 of the circuit in which the amplifying elements of the number the same as the number of the plurality of amplifiers are connected in series is larger than 0 dB.

10. The amplifier circuit according to claim 1 ,
wherein an output reflection coefficient of the amplifying element is larger than 0.75.

Assignees

• Fujitsu Ltd

Inventors

• Sato Masaru

Classifications

• H03F1/342

  in field-effect transistor amplifiers · CPC title

• H03F1/56

  Modifications of input or output impedances, not otherwise provided for · CPC title

• H03F3/601 Primary

  using FET's, e.g. GaAs FET's (H03F3/607, H03F3/608 take precedence) · CPC title

• H03F2200/72

  the amplifier stage being a common gate configuration MOSFET · CPC title

• H03F2200/405

  the output amplifying stage of an amplifier comprising more than three power stages · CPC title