Structure for an inductor-capacitor voltage-controlled oscillator

Patent metadata

Field	Value
Publication number	US-9281779-B2
Application number	US-201414491037-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Jan 4, 2013
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.

First claim

What is claimed is:

1. A circuit, comprising:
a first resistor coupled to a supply voltage;
a second resistor coupled to the first resistor via a first node;
a first field-effect transistor gate-coupled to the first node via a second node, wherein the first field-effect transistor is source-coupled to the supply voltage, and wherein the first field-effect transistor is drain-coupled to a third resistor via a third node;
a second field-effect transistor gate-coupled to the third node via a fourth node, wherein the second field-effect transistor is source-coupled to the supply voltage, and wherein the second field-effect transistor is drain-coupled to a fourth resistor via a fifth node; and
a third field-effect transistor gate-coupled to the fifth node via a sixth node, wherein the third field-effect transistor is source-coupled to the supply voltage, and wherein the third field-effect transistor is drain-coupled to a fifth resistor via a seventh node.

2. The circuit of claim 1 , further comprising:
a first oscillator node;
a second oscillator node; and
a compensating capacitive network coupled to the first oscillator node and the second oscillator node, wherein the circuit is coupled to the compensating capacitive network.

3. The circuit of claim 2 , wherein the compensating capacitive network compensates for a change in frequency of oscillation of the circuit caused by a supply voltage dependence of the circuit.

4. The circuit of claim 2 , wherein the circuit is coupled to the compensating capacitive network via an eighth node.

5. The circuit of claim 3 , further comprising:
a first capacitive network coupled to the first oscillator node and second oscillator node, wherein the first capacitive network is designed to allow the circuit to obtain an approximate target frequency of oscillation.

6. The circuit of claim 3 , wherein the voltage supply generates and supplies a voltage to the compensating capacitive network sufficient to allow the compensating capacitive network to compensate for a reduction in frequency of oscillation of the circuit.

7. The circuit of claim 3 , further comprising:
a second capacitive network coupled to the first oscillator node and the second oscillator node, wherein the second capacitive network allows the circuit to obtain a desired frequency of oscillation;
a filter coupled to the second capacitive network, wherein the filter supplies a voltage to the second capacitive network; and
a transconductor coupled to the first oscillator node and the second oscillator node, wherein the transconductor is designed to compensate for a change in the frequency of oscillation in the circuit.

8. The circuit of claim 1 , wherein the second resistor, third resistor, fourth resistor, and fifth resistor are ground coupled.

9. A design process comprising:
translating a hardware description language (HDL) design structure encoded on a tangible machine-readable data storage medium to a second design structure, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of an inductor-capacitor voltage-controlled oscillator, wherein said HDL design structure comprises a circuit including:
a first resistor coupled to a supply voltage;
a second resistor coupled to the first resistor via a first node; and
a first field-effect transistor gate-coupled to the first node via a second node, wherein the first field-effect transistor is source-coupled to the supply voltage, and wherein the first field-effect transistor is drain-coupled to a third resistor via a third node;
a second field-effect transistor gate-coupled to the third node via a fourth node, wherein the second field-effect transistor is source-coupled to the supply voltage, and wherein the second field-effect transistor is drain-coupled to a fourth resistor via a fifth node; and
a third field-effect transistor gate-coupled to the fifth node via a sixth node, wherein the third field-effect transistor is source-coupled to the supply voltage, and wherein the third field-effect transistor is drain-coupled to a fifth resistor via a seventh node.

10. The design process of claim 9 , wherein the HDL design structure further comprises:
a first oscillator node;
a second oscillator node; and
a compensating capacitive network coupled to the first oscillator node and the second oscillator node, wherein the sub-circuit is coupled to the compensating capacitive network.

11. The design process of claim 10 , wherein the compensating capacitive network compensates for a change in frequency of oscillation of the circuit caused by a supply voltage dependence of the circuit.

12. The design process of claim 10 , wherein the sub-circuit is coupled to the compensating capacitive network via an eighth node.

13. The design process of claim 11 , wherein the HDL design structure further comprises:
a first capacitive network coupled to the first oscillator node and second oscillator node, wherein the first capacitive network is designed to allow the circuit to obtain an approximate target frequency of oscillation.

14. The design process of claim 11 , wherein the voltage supply generates and supplies a voltage to the compensating capacitive network sufficient to allow the compensating capacitive network to compensate for a reduction in frequency of oscillation of the circuit.

15. The design process of claim 11 , wherein the HDL design structure further comprises:
a second capacitive network coupled to the first oscillator node and the second oscillator node, wherein the second capacitive network allows the circuit to obtain a desired frequency of oscillation;
a filter coupled to the second capacitive network, wherein the filter supplies a voltage to the second capacitive network; and
a transconductor coupled to the first oscillator node and the second oscillator node, wherein the transconductor is designed to compensate for a change in the frequency of oscillation in the circuit.

16. The design process of claim 9 , wherein the second resistor, third resistor, fourth resistor, and fifth resistor are ground coupled.

Assignees

• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Ainspan Herschel A
• Kelkar Ram
• Malladi Anjali R
• Malladi Ramana M

Classifications

• H03B2200/005

  including measures to switch a capacitor · CPC title

• H03B2202/042

  the circuit element belonging to the power supply · CPC title

• G06F30/30

  Circuit design · CPC title

• H03B5/1265 Primary

  switched capacitors · CPC title

• H03B5/1253

  the transistors being field-effect transistors · CPC title