Thin film transistor for integrated circuit

US9281409B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9281409-B2
Application numberUS-201414330444-A
CountryUS
Kind codeB2
Filing dateJul 14, 2014
Priority dateJul 16, 2013
Publication dateMar 8, 2016
Grant dateMar 8, 2016

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, a side surface of the second oxide semiconductor film, and a top surface of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode which is in contact with the gate insulating film and faces the top surface and the side surface of the second oxide semiconductor film, wherein a thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and wherein a difference between the thickness of the first oxide semiconductor film and the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm. 2. The semiconductor device according to claim 1 , wherein the difference between the thickness of the first oxide semiconductor film and the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm and smaller than or equal to 50 nm. 3. The semiconductor device according to claim 1 , wherein a channel width is smaller than or equal to 40 nm. 4. The semiconductor device according to claim 1 , wherein the semiconductor device further comprises a source electrode and a drain electrode each in contact with the top surface of the second oxide semiconductor film and a bottom surface of the third oxide semiconductor film. 5. The semiconductor device according to claim 1 , wherein the semiconductor device further comprises a conductive film below the insulating surface. 6. The semiconductor device according to claim 5 , wherein the conductive film is electrically connected to the gate electrode. 7. The semiconductor device according to claim 1 , wherein the gate insulating film is an insulating film containing at least one of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. 8. A semiconductor device comprising: a first oxide semiconductor film provided over a projected portion of an insulating surface comprising a depressed portion and the projected portion; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, a side surface of the second oxide semiconductor film, and a top surface of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode which is in contact with the gate insulating film and faces the top surface and the side surface of the second oxide semiconductor film, wherein a sum of a height of the projected portion of the insulating surface and a thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and wherein a difference between the sum of the height of the projected portion of the insulating surface and the thickness of the first oxide semiconductor film and the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm. 9. The semiconductor device according to claim 8 , wherein the difference between the thickness of the first oxide semiconductor film and the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm and smaller than or equal to 50 nm. 10. The semiconductor device according to claim 8 , wherein a channel width is smaller than or equal to 40 nm. 11. The semiconductor device according to claim 8 , wherein the semiconductor device further comprises a source electrode and a drain electrode each in contact with the top surface of the second oxide semiconductor film and a bottom surface of the third oxide semiconductor film. 12. The semiconductor device according to claim 8 , wherein the semiconductor device further comprises a conductive film below the insulating surface. 13. The semiconductor device according to claim 12 , wherein the conductive film is electrically connected to the gate electrode. 14. The semiconductor device according to claim 8 , wherein the gate insulating film is an insulating film containing at least one of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. 15. A semiconductor device comprising: a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, a side surface of the second oxide semiconductor film, and a top surface of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode which is in contact with the gate insulating film, wherein a thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and wherein a difference between the thickness of the first oxide semiconductor film and the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm. 16. The semiconductor device according to claim 15 , wherein the difference between the thickness of the first oxide semiconductor film and the sum of the thickness of the third oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm and smaller than or equal to 50 nm. 17. The semiconductor device according to claim 15 , wherein a channel width is smaller than or equal to 40 nm. 18. The semiconductor device according to claim 15 , wherein the semiconductor device further comprises a source electrode and a drain electrode each in contact with the top surface of the second oxide semiconductor film and a bottom surface of the third oxide semiconductor film. 19. The semiconductor device according to claim 15 , wherein the semiconductor device further comprises a conductive film below the insulating surface. 20. The semiconductor device according to claim 19 , wherein the conductive film is electrically connected to the gate electrode. 21. The semiconductor device according to claim 15 , wherein the gate insulating film is an insulating film containing at least one of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

Assignees

Inventors

Classifications

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

  • comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

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What does patent US9281409B2 cover?
A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insu…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6756. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).