Embedded on-chip security

Patent metadata

Field	Value
Publication number	US-9281236-B2
Application number	US-201514718128-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	Sep 20, 2013
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.

First claim

What is claimed is:

1. An integrated circuit comprising:
a reset input and a clock input;
a circular shift logic, for use in producing circularly shifting test patterns, wherein the
circular shift logic comprises the reset and clock input and one or more outputs and complement outputs, wherein the one or more outputs are operatively connected with the reset input and the clock input, and wherein each output corresponds to a complement output;
a plurality of n-channel metal-oxide-semiconductor field-effect transistors (nMOSFET),
wherein a nMOSFET comprises a gate, a source, and a drain, wherein the source is operatively connected with zero voltage, the gate is operatively connected with an output of the circular shift logic, and the drain is operatively connected with a conductive element of the randomly patterned interconnect structure; and
a plurality of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFET),
wherein each pMOSFET corresponds to a nMOSFET, and wherein the pMOSFET is operatively connected with a conductive element of the randomly patterned interconnect structure adjacent to the conductive element operatively connected with the corresponding nMOSFET, and wherein a pMOSFET comprises a gate, a source, and a drain, wherein the source is operatively connected with a voltage source, the gate is operatively connected with a complement output of the circular shift logic, and the drain is operatively connected with a conductive element of the randomly patterned interconnect structure.

2. The integrated circuit of claim 1 , wherein one output of the circular shift logic is at logic high and rest of the outputs are at logic lows.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Feng Kai D
• Li Wai-Kin
• Wang Ping-Chuan
• Yang Zhijian

Classifications

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title