Wafer handling systems and methods

US9281222B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9281222-B2
Application numberUS-201414203237-A
CountryUS
Kind codeB2
Filing dateMar 10, 2014
Priority dateMar 15, 2013
Publication dateMar 8, 2016
Grant dateMar 8, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A wafer handling system may include upper and lower linked robot arms that may move a wafer along a nonlinear trajectory between chambers of a semiconductor processing system. These features may result in a smaller footprint in which the semiconductor processing system may operate, smaller transfer chambers, smaller openings in process chambers, and smaller slit valves, while maintaining high wafer throughput. In some embodiments, simultaneous fast wafer swaps between two separate chambers, such as load locks and ALD (atomic layer deposition) carousels, may be provided. Methods of wafer handling are also provided, as are other aspects.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer handling system, comprising: a robot including a first arm having a first length and a second arm having a second length greater than the first length and less than twice the first length, the second arm rotatable about its center; wherein the robot is configured to move a wafer such that the center of the wafer moves along a nonlinear trajectory. 2. The wafer handling system of claim 1 , wherein the first arm is an upper arm and the second arm is a lower arm. 3. The wafer handling system of claim 1 , wherein the robot is configured to move a wafer such that the center of the wafer moves along a curved trajectory about the center of the second arm. 4. The wafer handling system of claim 1 , wherein the first arm is rotatably coupled to a first end of the second arm. 5. The wafer handling system of claim 1 , wherein the first arm is configured to carry a wafer. 6. The wafer handling system of claim 1 , further comprising a third arm having a third length, wherein the second length is greater than the third length and less than twice the third length. 7. The wafer handling system of claim 6 , wherein the third arm is rotatably coupled to a second end of the second arm. 8. The wafer handling system of claim 6 , wherein the third arm is configured to carry a wafer. 9. The wafer handling system of claim 6 , wherein the robot is configured to move a first wafer carried by the first arm such that the center of the first wafer moves along a first nonlinear trajectory and concurrently move a second wafer carried by the third arm such that the center of the second wafer moves along a second nonlinear trajectory, the first nonlinear trajectory located between two chambers and the second nonlinear trajectory located between the same two chambers. 10. A semiconductor processing system, comprising: a first chamber configured to receive one or more wafers; a second chamber configured to receive one or more wafers; and a robot located between the first chamber and the second chamber, the robot including a first arm having a first length and a second arm having a second length greater than the first length and less than twice the first length, the second arm rotatable about its center; wherein: the robot is configured to move a wafer to or from the first chamber and from or to the second chamber such that the center of the wafer moves along a nonlinear trajectory between the first chamber and the second chamber. 11. The semiconductor processing system of claim 10 , wherein the robot is configured to move a wafer to or from the first chamber and from or to the second chamber such that the center of the wafer moves along a first linear portion of the nonlinear trajectory for a first distance, along a curved portion of the nonlinear trajectory around the center of the second arm for a second distance, and along a second linear portion of the nonlinear trajectory for a third distance. 12. The semiconductor processing system of claim 10 , wherein the first arm is rotatably coupled to a first end of the second arm and is configured to carry a wafer. 13. The semiconductor processing system of claim 10 , further comprising a third arm having a third length, wherein: the second length is greater than the third length and less than twice the third length; the third arm is rotatably coupled to a second end of the second arm; and the third arm is configured to carry a wafer. 14. The semiconductor processing system of claim 10 , wherein the first chamber is a processing chamber and the second chamber is a load lock chamber. 15. The semiconductor processing system of claim 10 , wherein the robot further includes a third arm having a third length, wherein the second length is greater than the third length and less than twice the third length, and the robot is configured to move a first wafer carried by the first arm such that the center of the first wafer moves along a first nonlinear trajectory and concurrently move a second wafer carried by the third arm such that the center of the second wafer moves along a second nonlinear trajectory, the robot configured to move first wafer and the second wafer concurrently between the first chamber and the second chamber. 16. A method of transferring wafers in a semiconductor processing system, comprising: providing a robot configured to transfer a first wafer, the robot comprising a first arm coupled to a second arm, wherein the first arm has a first length and the second arm has a second length greater than the first length and less than twice the first length, the second arm rotatable about its center; and moving the first wafer with the robot such that the center of the first wafer moves along a nonlinear trajectory. 17. The method of claim 16 , wherein the moving the first wafer comprises: moving the first wafer with the robot such that the center of the first wafer moves along a first linear portion of the nonlinear trajectory for a first distance; moving the first wafer with the robot such that the center of the first wafer moves along a curved portion of the nonlinear trajectory around the center of the second arm for a second distance; and moving the first wafer with the robot such that the center of the first wafer moves along a third linear portion of the nonlinear trajectory for a third distance. 18. The method of claim 16 , wherein the providing a robot further comprises providing a robot comprising a third arm having a third length, wherein the second length of the second arm is greater than the third length and less than twice the third length. 19. The method of claim 16 , wherein the moving the first wafer comprises moving the first wafer with the robot such that the center of the first wafer moves along a curved trajectory from a first chamber to a second chamber. 20. The method of claim 16 , further comprising moving a second wafer concurrently with the first wafer with the robot such that the center of the second wafer moves along a second nonlinear trajectory, the first wafer moving between two chambers and the second wafer moving concurrently between the same two chambers.

Assignees

Inventors

Classifications

  • Mechanical parts of transfer devices · CPC title

  • characterised by the construction of the transfer chamber · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9281222B2 cover?
A wafer handling system may include upper and lower linked robot arms that may move a wafer along a nonlinear trajectory between chambers of a semiconductor processing system. These features may result in a smaller footprint in which the semiconductor processing system may operate, smaller transfer chambers, smaller openings in process chambers, and smaller slit valves, while maintaining high w…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/0464. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).