Wafer and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9281189-B2
Application number	US-201214354858-A
Country	US
Kind code	B2
Filing date	Oct 26, 2012
Priority date	Oct 26, 2011
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.

First claim

The invention claimed is:

1. A method of manufacturing a thin film, the method comprising:
growing an epitaxial layer on a surface of a wafer at a growth temperature,
wherein the growing of the epitaxial layer comprises controlling a defect present on the surface of the wafer, and
the controlling of the detect comprises maintaining the wafer at a first temperature higher than the growth temperature; and
maintaining the wafer at a second temperature lower than the growth temperature;
wherein the wafer includes silicon carbide;
wherein the epitaxial layer includes silicon carbide;
wherein the growing of the epitaxial layer comprises increasing a temperature of the wafer to the growth temperature before the growing of the epitaxial layer, wherein the increasing of the temperature of the wafer comprises a first ramp-up and a second ramp-up; and
wherein a temperature of the second ramp-up is higher than a temperature of the first ramp-up.

2. The method of claim 1 , wherein the controlling of the defect is performed at an initial stage of the growing of the epitaxial layer.

3. The method of claim 1 , wherein, in the controlling of the defect, a buffer layer for controlling the defect is grown.

4. The method of claim 1 , wherein, in the controlling of the defect, the maintaining of the wafer at the first temperature and the maintaining of the wafer at the second temperature are alternately performed.

5. The method of claim 1 , wherein the maintaining of the wafer at the first temperature and the maintaining of the wafer at the second temperature are performed at least one time.

6. The method of claim 1 , wherein the first temperature is higher than the growth temperature by 5° C. to 50° C.

7. The method of claim 1 , wherein the second temperature is lower than the growth temperature by 5° C. to 50° C.

8. The method of claim 1 , wherein the maintaining of the wafer at the first temperature is performed for less than 5 minutes.

9. The method of claim 1 , wherein the controlling of the defect is performed at a hydrogen atmosphere.

10. The method of claim 1 , wherein a thickness of a buffer layer is 1 μm to 10 μm.

11. A wafer manufactured according to the method of claim 1 .

12. A wafer manufactured according to the method of claim 2 .

13. A wafer manufactured according to the method of claim 3 .

14. A wafer manufactured according to the method of claim 4 .

15. A wafer manufactured according to the method of claim 5 .

16. A wafer manufactured according to the method of claim 6 .

17. The wafer of claim 11 , wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm 2 .

18. The wafer of claim 17 , wherein a surface dislocation density of the epitaxial layer is equal to or less than 1/cm 2 .

Assignees

• Kim Moo Seong
• Lg Innotek Co Ltd

Inventors

• Kim Moo Seong

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/3246

  Monolayers · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title