Three-dimensional semiconductor devices

Patent metadata

Field	Value
Publication number	US-9281019-B2
Application number	US-201314057669-A
Country	US
Kind code	B2
Filing date	Oct 18, 2013
Priority date	Dec 10, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
bit lines provided on a substrate;
a gate structure provided between the substrate and the bit lines;
a common source line provided between the gate structure and the bit lines; and
channel pipes connecting the bit lines to the common source line,
wherein each of the channel pipes comprises a pair of vertical portions penetrating the gate structure and a horizontal portion connecting the vertical portions, and
wherein, in plan view, the pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

2. The device of claim 1 , wherein in each of the channel pipes, one of the pair of vertical portions is connected to one of the bit lines, and the other is connected to the common source line.

3. The device of claim 1 , wherein the horizontal portion extends in a longitudinal direction that defines an angle relative to a direction in which the bit lines extend.

4. The device of claim 3 , wherein the angle is about 3 degrees to about 45 degrees.

5. The device of claim 1 , wherein the gate structure further comprises:
at least one string selection line interposed between the gate structure and the bit lines; and
a ground selection line interposed between the gate structure and the common source line,
wherein the at least one string selection line is provided to the bit lines.

6. The device of claim 5 , wherein the gate structure further comprises a plurality of word lines, and wherein the string selection line and the word lines have a same width.

7. The device of claim 5 , wherein a number of the channel pipes penetrating the string selection line is equal to a number of the bit lines crossing over the string selection line.

8. A three-dimensional memory device, comprising:
a plurality of bit lines extending in a first direction on a substrate and a common source line extending in a second direction on the substrate; and
a plurality of channel pipes on the substrate connecting the common source line to ones of the bit lines, the channel pipes respectively comprising a pair of columnar portions protruding from the substrate and a coupling portion extending therebetween,
wherein, along the first direction, adjacent ones of the channel pipes are connected to different ones of the bit lines.

9. The device of claim 8 , wherein, along the second direction, the bit lines equal or outnumber the channel pipes.

10. The device of claim 9 , wherein, along the second direction, adjacent ones of the channel pipes are connected to alternating ones of the bit lines, respectively.

11. The device of claim 10 , wherein, along the second direction, respective ones of the pair of columnar portions of each of the adjacent ones of the channel pipes are connected to the alternating ones of the bit lines, respectively.

12. The device of claim 11 , wherein, along the second direction, respective other ones of the pair of columnar portions of each of the adjacent ones of the channel pipes are connected to the common source line.

13. The device of claim 12 , wherein, along the second direction, the respective other ones of the pair of columnar portions of each of the adjacent ones of the channel pipes overlap with ones of the bit lines between the alternating ones thereof, respectively, in plan view.

14. The device of claim 8 , wherein the coupling portion of the respective channel pipes extends in a third direction that defines a non-parallel angle relative to the first direction of the bit lines.

15. The device of claim 14 , wherein the coupling portion of each of the channel pipes overlaps with two of the bit lines in plan view.

16. The device of claim 15 , wherein the third direction defines a non-perpendicular angle relative to the second direction of the common source line.

17. The device of claim 8 , further comprising:
a gate structure between the bit lines and the substrate, the gate structure comprising:
a plurality of word lines adjacent sidewalls of the columnar portions of the channel pipes and extending in the second direction, wherein the columnar portions respectively comprise a semiconductor layer and a memory layer thereon;
a string selection line extending in the second direction between the plurality of word lines and the bit lines; and
a ground selection line extending in the second direction between the plurality of word lines and the common source line.

18. The device of claim 17 , wherein the string selection line and/or the ground selection line have a same width as the word lines along the first direction.

19. The device of claim 17 , wherein the string selection line and/or the ground selection line have a narrower width than the word lines along the first direction.

Assignees

• Park Jintaek
• Park Youngwoo
• Samsung Electronics Co Ltd

Inventors

• Park Jintaek
• Park Youngwoo

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H01L45/146

  Electricity · mapped topic

• H01L45/148

  Electricity · mapped topic