Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track

Patent metadata

Field	Value
Publication number	US-9280995-B2
Application number	US-201414244846-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Mar 28, 2014
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value.

First claim

The invention claimed is:

1. A mass storage system comprising:
a rotating magnetic storage media having adjacent servo address marks written in a spiral pattern of servo address marks on the storage media;
a head configured to read data and servo information stored on the media, the head and the spiral pattern configured such that the head reads a plurality of adjacent servo address marks each time the head encounters the spiral pattern of servo address marks;
a servo address mark detector coupled to the head and configured to detect servo address marks when read by the head;
a counter driven by a system clock;
a latch responsive to an output of the servo address mark detector and configured to sample a count value of the counter when triggered by the servo address mark detector; and
a disk-locked clock synthesizer, responsive to the latch, configured to generate the system clock;
wherein the synthesizer, as the head reads the plurality of adjacent servo address marks, is configured to:
calculate differences in value between successively sampled count values from the latch;
average the differences in value to create an average difference value;
normalize a difference between the average difference value and a target value to create a phase error value; and
update a phase of the system clock in response to the phase error value.

2. The mass storage system of claim 1 wherein a plurality of the spiral patterns of servo address marks are written on the storage media, the spiral patterns spaced such that, for a constant rotational speed of the storage media, a time interval (Tspiral) the head experiences between spirals is substantially the same regardless of what radius the head is over the storage media, and wherein the counter is designed overflow at the same rate as the time interval Tspiral.

3. The mass storage system of claim 1 wherein the head and the spiral pattern are configured such that the head reads a known number greater than one of adjacent servo address marks each time the head encounters the spiral pattern of servo address marks.

4. The mass storage system of claim 1 wherein the head reads the plurality of adjacent servo address marks using one of a timed window where servo address marks are detected only during the timed window, or before a time-out occurs during which no servo address mark is detected by the detector.

5. The mass storage system of claim 1 wherein the phase error is calculated in accordance with:
(TARGET−AVE_SAMP DIFF)/TARGET;

where TARGET is a desired average difference value when the system clock is locked to the servo address marks, and AVE — SAMP DIFF is an actual average difference count value.

6. The mass storage system of claim 1 wherein the synthesizer comprises a phase-locked loop generating the system clock, the phase locked loop responsive to the phase error signal and a reference clock.

7. The mass storage system of claim 1 wherein the synthesizer further comprises a processor configured to control the phase locked loop, responsive to the detector and the latch, and perform the steps recited in claim 1 .

8. The mass storage system of claim 1 wherein the processor is one of a programmable computer, a state machine, and a combination thereof.

9. The mass storage system of claim 1 wherein the synthesizer, prior to phase locking the system clock to the servo address marks, the phase error is set to zero.

10. The mass storage system of claim 1 wherein the spiral pattern of servo address marks comprises an alternating sequence of preamble and servo address mark bit patterns, and the servo address mark detector is a pattern detector configured to detect the preamble and servo address marks bit patterns.

11. The mass storage system of claim 1 wherein the servo address mark detector comprises:
a slicer, coupled to the head, configured to slice signals from the head to generate sliced data;
a shift register configured to receive and serially shift the sliced data therein; and
a comparator, coupled to the shift register, configured to compare the sliced data in the shift register with a pre-established bit pattern;
wherein the comparator triggers the output of the servo address mark detector when the sliced data in the shift register matches the pre-established bit pattern.

12. A method for phase locking a system clock to servo address marks in a mass storage system having a rotating magnetic storage media and head over the media for reading data and servo information thereon, the rotating magnetic storage media having adjacent servo address marks written in a spiral pattern of servo address marks on the storage media, and a counter driven by a system clock, the method comprising the steps of:
reading, by the head, a plurality of adjacent servo address marks each time the head encounters the spiral pattern of servo address marks;
detecting each of adjacent servo address marks read by the head;
sampling the counter, via a latch, to obtain a sampled count value each time a servo address mark is detected;
calculating differences in value between successive sampled count values from the latch;
averaging the differences in value to create an average difference value;
normalizing a difference between the average difference value and a target value to create a phase error value;
and updating a phase of the system clock in response to the phase error value.

13. The method of claim 12 wherein a plurality of the spiral patterns of servo address marks are written on the storage media, the spiral patterns spaced such that, for a constant rotational speed of the storage media, a time interval (Tspiral) the head experiences between spirals is substantially the same regardless of what radius the head is over the storage media, and wherein the counter is designed overflow at the same rate as the time interval Tspiral.

14. The method of claim 12 wherein the head and the spiral pattern are configured such that the head reads a known number greater than one of adjacent servo address marks each time the head encounters the spiral pattern of servo address marks.

15. The method of claim 12 wherein the head reads the plurality of adjacent servo address marks using one of a timed window where servo address marks are detected only during the timed window, or before a time-out occurs during which no servo address mark is detected by the detector.

16. The method of claim 12 wherein in the step of normalizing, the phase error is calculated in accordance with:
(TARGET−AVE_SAMP DIFF)/TARGET;

where TARGET is a desired average difference value when the system clock is locked to the servo address marks, and AVE — SAMP DIFF is an actual average difference count value.

17. The method of claim 12 wherein the synthesizer, prior to phase locking the system clock to the servo address marks, the phase error is set to zero.

18. The method of claim 12 wherein the spiral pattern of servo address marks comprises an alternating sequence of preamble and servo address mark bit patterns, and the step of detecting each of adjacent servo address marks read by the head comprises the step of detecting the preamble and servo address marks bit patterns.

19. The method of claim 12 wherein the step of detecting each of adjacent servo address marks read by the head comprises the steps of:
slicing signals from the head to generate sliced data;
serially shifting the sliced data into a shift register; and
comparing the sliced data in the shift register with a pre-established bit pattern;
wherein the serv

Assignees

• Lsi Corp
• Avago Technologies General Ip

Inventors

• Fan Xiangdong
• Chen Songtao

Classifications

• G11B5/59627

  Aligning for runout, eccentricity or offset compensation (G11B5/5534, G11B5/59677, G11B5/59688 take precedence) · CPC title

• G11B5/59661

  Spiral servo format · CPC title

• G11B5/59644 Primary

  Acquisition or selection of servo format from a system reference (after track seek G11B5/5556) · CPC title

• G11B2220/2516

  Hard disks · CPC title

• G11B20/10222

  clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation (dedicated sync patterns in the modulation code G11B20/1403) · CPC title