System and method for clock network meta-synthesis

Patent metadata

Field	Value
Publication number	US-9280628-B2
Application number	US-201113214859-A
Country	US
Kind code	B2
Filing date	Aug 22, 2011
Priority date	Aug 22, 2011
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

First claim

What is claimed is:

1. A two-phase method of constructing a clock network comprising:
receiving design specifications for a clock network at a meta-synthesis tool in a metasynthesis phase of the two-phase method, the meta-synthesis phase providing an abstraction of the clock network, wherein the meta-synthesis tool is configured to:
determine a topology of the clock network based on the design specifications, the topology indicating at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level;
determine design parameters for the clock network based on the determined topology;
generate a clock network synthesis tool specification file that includes the design parameters, the clock network synthesis tool specification file generated as input to a clock network synthesis tool; and
synthesizing, by the clock network synthesis tool in a synthesis phase of the two-phase method, the clock network according to the clock network synthesis tool specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network, the synthesis phase providing an implementation of the clock network.

2. The method of claim 1 , wherein the design specifications comprise at least one of a fanout range of the clock network, a set of buffer types for the clock network and a set of endpoints for the clock network.

3. The method of claim 1 , wherein the determined topology further indicates that the buffer type of a first buffer included in a particular level is the same as the buffer type of a second buffer included in the particular level.

4. The method of claim 1 , wherein the determined topology further indicates that the buffer fanout of a first buffer included in a particular level is the same as the buffer fanout of a second buffer included in the particular level.

5. The method of claim 1 , wherein the determined topology further indicates paths from the clock generator to each endpoint of the clock network, wherein the paths are replicas of each other.

6. The method of claim 1 , wherein the determined topology further indicates an even number of levels of the clock network.

7. The method of claim 1 , wherein the buffer type IS restricted to a predefined set of buffer types as indicated in the design specifications.

8. The method of claim 1 , wherein determining the topology further comprises determining a configuration of buffers for each level of the clock network based on the design specifications.

9. The method of claim 1 , wherein the determined design parameters include at least one of the plurality of levels of the clock network, the buffer type for each level and the buffer fanout for buffers included in each level as indicated by the topology.

10. The method of claim 1 , wherein the determined topology comprises a clock tree split as far from the clock signal as allowed by the design specifications.

11. An article of manufacture for constructing a clock network, comprising:
a computer readable medium; and
first computer-executable instructions carried on the computer readable medium, the instructions readable by a processor, the instructions, when read and executed, causing the processor to implement a meta-synthesis tool, the meta-synthesis tool providing an abstraction of the clock network and configured to:
receive design specifications for a clock network;
determine a topology of the clock network based on the design specifications, the topology indicating at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level;
determine design parameters for the clock network based on the determined topology; and
generate a clock network synthesis tool specification file that includes the design parameters, the clock network synthesis tool specification file usable as input to a clock network synthesis tool;

second computer-executable instructions carried on the computer readable medium, the instructions readable by a processor, the instructions, when read and executed, causing the processor to implement a clock network synthesis tool, the clock network synthesis tool providing an implementation of the clock network and configured to:
synthesize, according to the clock network synthesis tool specification file, the clock network to include the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

12. The article of manufacture of claim 11 , wherein the design specifications comprise at least one of a fanout range of the clock network, a set of buffer types for the clock network and a set of endpoints for the clock network.

13. The article of manufacture of claim 11 , wherein the determined topology further indicates that the buffer type of a first buffer included in a particular level is the same as the buffer type of a second buffer included in the particular level.

14. The article of manufacture of claim 11 , wherein the determined topology further indicates that the buffer fanout of a first buffer included in a particular level is the same as the buffer fanout of a second buffer included in the particular level.

15. The article of manufacture of claim 11 , wherein the determined topology further indicates paths from the clock generator to each endpoint of the clock network, wherein the paths are replicas of each other.

16. The article of manufacture of claim 11 , wherein the determined topology further indicates an even number of levels of the clock network.

17. The article of manufacture of claim 11 , wherein the buffer type is restricted to a predefined set of buffer types as indicated in the design specifications.

18. The article of manufacture of claim 11 , wherein the processor is further caused to determine the topology by determining a configuration of buffers for each level of the clock network based on the design specifications.

19. The article of manufacture of claim 11 , wherein the determined design parameters include at least one of the plurality of levels of the clock network, the buffer type for each level and the fanout for buffers included in each level as indicated by the topology.

20. The article of manufacture of claim 11 , wherein the determined topology comprises a clock tree split as far from the clock signal as allowed by the design specifications.

Assignees

• Walker William
• Reddy Subodh M
• Fujitsu Ltd

Inventors

• Walker William
• Reddy Subodh M

Classifications

• G06F30/396 Primary

  Clock trees · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F2217/62

  Physics · mapped topic