Memory system and host device
US-2024394189-A1 · Nov 28, 2024 · US
US9280474B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9280474-B2 |
| Application number | US-201313976325-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 3, 2013 |
| Priority date | Jan 3, 2013 |
| Publication date | Mar 8, 2016 |
| Grant date | Mar 8, 2016 |
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A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: determining a value for a stride length (L) in response to detecting a stride pattern in memory operations; prefetching data for expected memory operations based on a prefetch address determined based on a base memory address, the stride length L, and a prefetch distance (D), wherein the prefetch address is given by a sum of the base memory address and a product (L×D); maintaining a miss prefetch count (C) indicative of a number of…
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