Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US9280299B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9280299-B2 |
| Application number | US-201414164695-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 27, 2014 |
| Priority date | Dec 16, 2009 |
| Publication date | Mar 8, 2016 |
| Grant date | Mar 8, 2016 |
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A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
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The invention claimed is: 1. An apparatus, comprising: a memory, wherein the memory includes a plurality of regions, wherein each region of the plurality of regions includes a plurality of blocks, and wherein each block of the plurality of blocks includes a plurality of memory cells; and a controller coupled to the memory, wherein the controller is configured to: assign a first over-provisioning ratio to a first region of the plurality of regions; assign a second over-provis…
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