Nano-electro-mechanical-switch adiabatic dynamic logic circuits

Patent metadata

Field	Value
Publication number	US-9276578-B2
Application number	US-201314010195-A
Country	US
Kind code	B2
Filing date	Aug 26, 2013
Priority date	Aug 31, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.

First claim

The invention claimed is:

1. A dynamic logic gate, comprising:
one or more four-terminal, nano-electro-mechanical-switches (NEMS);
each NEMS having a body electrode, a source electrode, a gate electrode, and a drain electrode, the source electrode being selectively electrically connected to the drain electrode, as a function of tension between the gate electrode and the body electrode;
wherein the body electrode of each NEMS is biased to a negative bias voltage (V b ) having an absolute value of min{V po }, where V po is a set of varying pull-off voltages of all NEMS in the dynamic logic gate due to process variations, wherein a given pull-off voltage V po comprises an absolute value of an applied gate-to-body voltage |V gb | that results in the source electrode from being electrically disconnected from the drain electrode, and such that an applied ground voltage (0V) to the gate electrode results in pull-off of any of the NEMS; and
wherein a power supply voltage (V dd ) is set to a value corresponding to the expression: max{V pi }−min{V po }, where V pi is a set of varying pull-in voltages of all NEMS in the dynamic logic gate due to process variations, and wherein a given pull-in voltage V pi comprises an absolute value of an applied gate-to-body voltage |V gb | that results in the source electrode from being electrically connected to the drain electrode.

2. The dynamic logic gate of claim 1 , further comprising a time-varying power for supplying a timing-varying power clock signal to the nano-electro-mechanical-switch.

3. The dynamic logic gate of claim 2 , wherein the time-varying power clock signal is one of a sinusoidal signal and a trapezoidal signal.

4. A dynamic logic cascade circuit comprising single-rail dynamic logic gates, comprising at least one dynamic logic gate according to claim 1 , wherein the dynamic logic cascade circuit generates a single logic output.

5. The dynamic logic cascade circuit according to claim 4 , comprising four dynamic logic gates coupled to four respective power sources for providing the four dynamic logic gates with respective time-varying power clock signals.

6. The dynamic logic cascade circuit according to claim 5 , wherein the four power clock signals are out-of-phase by 90 degrees.

7. The dynamic logic cascade circuit according to claim 5 , wherein each of the four time-varying power clock signals comprises four equal timing intervals, respectively corresponding to pre-charge, hold, evaluate and latch periods.

8. A dynamic logic cascade circuit comprising dual-rail dynamic logic gates, comprising at least one dynamic logic gate according to claim 1 , wherein the dynamic logic cascade circuit generates a logic output and its complementary output.

9. A dynamic logic cascade circuit according to claim 8 , comprising two cross-coupled dynamic logic gates for latching output signals.

10. A dynamic logic cascade circuit according to claim 8 , further comprising a dynamic logic gate for initializing output signals.

11. A dynamic logic cascade circuit according to claim 8 , comprising four dual-rails of dynamic logic gates and four respective power sources for providing the four dual-rails of dynamic logic gates with respective time-varying power clock signals.

Assignees

• IBM

Inventors

• Despont Michel
• Grogg Daniel
• Hagleitner Christoph
• Pu Yu

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/02 Primary

  using specified components ({H03K19/0005 - H03K19/0021}, H03K19/003 - H03K19/0175 take precedence) · CPC title