Dual edge-triggered retention flip-flop

Patent metadata

Field	Value
Publication number	US-9276566-B2
Application number	US-201414468343-A
Country	US
Kind code	B2
Filing date	Aug 26, 2014
Priority date	Dec 31, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.

First claim

What is claimed is:

1. A flip-flop comprising:
a first latch and a second latch, disposed on a substrate, wherein each of the first and second latches has an input coupled to an input pin, wherein the first latch is arranged to latch a first state of the input pin in response to a positive transition of a clock signal, wherein the second latch is arranged to latch a second state of the input pin in response to a negative transition of the clock signal; and
a data state retention latch, disposed on the substrate, wherein the data state retention latch in a normal operating mode is arranged to latch the output of the first latch in response to a first transition of the clock signal and to latch the output of the second latch in response to a second transition of the clock signal that is opposite in direction to the first transition, and wherein the data state retention latch in a low-power operating mode is arranged to maintain a latched input state of for a length of time that exceeds a period of the clock signal.

2. The flip-flop according to claim 1 , wherein the flip-flop is arranged during the low-power mode to maintain the output state of the data state retention latch over a period of time that includes a positive transition of the clock signal and an adjacent negative transition of the clock signal.

3. The flip-flop according to claim 1 , wherein the flip-flop is arranged to leave the normal operating mode and enter the low-power operating mode while the clock signal is in a high state.

4. The flip-flop according to claim 3 , wherein the flip-flop is arranged to set the logic state of at least one of the first and second latches in response to entering the normal operating mode.

5. The flip-flop according to claim 1 wherein the first and second latches have outputs that are gated by a signal that indicates the presence of the low-power operating mode.

6. The flip-flop according to claim 1 , wherein the first and second latches are powered down during the low-power operating mode.

7. The flip-flop according to claim 1 , wherein the first and second latches are arranged to latch a state of the input pin using transmission gates that are arranged to be gated by a signal that indicates the low-power operating mode.

8. The flip-flop according to claim 1 , wherein the data state retention latch is arranged to maintain an active state during a low-power operating mode, wherein the data state retention latch is not power gated during the active state during the low-power operating mode.

9. The flip-flop according to claim 8 , wherein the data state retention latch is arranged using transistors formed by a design process that has a higher voltage threshold than transistors used to form at least one of the first and second input latches, and wherein the data state retention latch is arranged to remain powered-up during the low-power operating mode.

10. The flip-flop according to claim 1 , comprising a multiplexer that is arranged to select between the first input and a second input, wherein the latched first state is latched by latching a first state of the second input in response to a positive transition of the clock signal, and wherein the latched second state is latched by latching a second state of the second input in response to a negative transition of the clock signal.

11. A system comprising a flip-flop disposed on a substrate and comprising
alternating input latches and an output latch, wherein the alternating input latches include a first input latch that is arranged to latch a first state of a first input in response to a first edge of a clock signal and a second input latch that is arranged to latch a second state of the first input in response to a second edge of the clock signal, wherein the output latch is coupled to each of the outputs of the alternating input latches, and wherein the output latch is arranged to retain the latched first state or the latched second state during a low-power mode; and
a power distribution system that is arranged to selectively apply power to the alternating input latches and to the output latch during a normal operating mode and to decouple power from the alternating input latches during a low-power operating mode.

12. The system according to claim 11 , wherein the state of the output latch is latched while transitioning from the low-power operating mode by at least one of the alternating latches in response to reconnecting power to the dual edge triggered circuit.

13. The system according to claim 11 , wherein the first and second latches are arranged to latch the state of first input by using transmission gates that are arranged to be gated by a signal that indicates the low-power operating mode.

14. The system according to claim 11 , wherein the output latch is arranged to maintain an active output during the low-power operating mode.

15. A method comprising:
latching in a first latch a first logic state of an input in response to a first edge of a clock signal;
latching in a second latch a second logic state of the input in response to a second edge of the clock signal, wherein the second edge transitions in a direction that is opposite the first edge;
latching in an output latch one of the latched output states of the first and second latches in response to an assertion of a signal that indicates a low-power operating mode;
maintaining the output state of the output latch in response to the assertion of a signal that indicates a low-power operating mode; and
conserving power in the first and second latches during the low-power operating mode.

16. The method of claim 15 , wherein the conserving power includes removing power from the in the latches used to latch the first and second states.

17. The method of claim 16 , comprising using the latched output state of the output latch to initialize at least one of the first and second latches before transitioning from the low-power operating mode.

Assignees

• Texas Instruments Inc

Inventors

• Singhal Vipul Kumar

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title