Duty ratio correction circuit and phase synchronization circuit

Patent metadata

Field	Value
Publication number	US-9276565-B2
Application number	US-201414566837-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Jan 24, 2014
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.

First claim

What is claimed is:

1. A duty ratio correction circuit comprising:
a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal;
a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction;
a first capacitor; and
a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.

2. The duty ratio correction circuit according to claim 1 , further comprising:
a first current source; and
a second current source, wherein
the first charge-discharge control circuit charges the first capacitor with a current of the first current source, and discharges the first capacitor by a current of the second current source.

3. The duty ratio correction circuit according to claim 2 , further comprising:
a second capacitor; and
a second charge-discharge control circuit configured to selectively charge or discharge the second capacitor based on the third signal, to generate a second control signal, wherein
the first current source or the second current source is a variable current source having a current value varied based on a signal difference between the first control signal and the second control signal.

4. The duty ratio correction circuit according to claim 3 , wherein the second charge-discharge control circuit charges the second capacitor with a current of the first current source and discharges the second capacitor by a current of the second current source.

5. The duty ratio correction circuit according to claim 3 , wherein the second signal is formed of a first polarity signal and a second polarity signal, the waveform shaping section includes
a first waveform shaping section configured to shape a waveform of the first polarity signal to generate a third polarity signal that is a target of the duty ratio correction, and
a second waveform shaping section configured to shape a waveform of the second polarity signal to generate a fourth polarity signal that is a target of the duty ratio correction, and
the first charge-discharge control circuit includes
a first transistor configured to connect or disconnect a connection between the first current source and the first capacitor, based on the third polarity signal, and
a second transistor configured to connect or disconnect a connection between the second current source and the first capacitor, based on the fourth polarity signal.

6. The duty ratio correction circuit according to claim 3 , wherein the first charge-discharge control circuit includes
a first transistor configured to connect or disconnect a connection between the first current source and the first capacitor, based on the third signal, and
a second transistor configured to connect or disconnect a connection between the second current source and the first capacitor, based on the third signal.

7. The duty ratio correction circuit according to claim 5 , wherein the second charge-discharge control circuit includes
a third transistor interposed between the first current source and the second capacitor, the third transistor being put into a connection state during a period in which the first transistor is put into a disconnection state, and
a fourth transistor interposed between the second current source and the second capacitor, the fourth transistor being put into a connection state during a period in which the second transistor is put into a disconnection state.

8. A phase synchronization circuit comprising:
a phase comparison circuit configured to compare a phase of an input clock signal with a phase of a feedback clock signal;
an oscillation circuit configured to generate a first signal based on a comparison result of the phase comparison circuit;
a frequency dividing circuit configured to divide a frequency of the first signal to generate the feedback clock signal; and
a duty ratio correction circuit configured to operate based on the first signal, wherein
the duty ratio correction circuit includes
a buffer circuit configured to generate a second signal based on the first signal, the second signal having a DC component corresponding to a first control signal,
a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction,
a first capacitor, and
a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.

Assignees

• Sony Corp

Inventors

• Tomita Kazutoshi
• Harada Shingo
• Niwa Atsumi

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title