Reservoir capacitor and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-9276500-B2
Application number	US-201314106792-A
Country	US
Kind code	B2
Filing date	Dec 15, 2013
Priority date	Aug 23, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

First claim

What is claimed is:

1. A reservoir capacitor, comprising:
a first capacitor group having at least two capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal;
a second capacitor group having at least two capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal; and
a connection line suitable for electrically coupling a first coupling node between the at least two capacitors included in the first capacitor group to a second coupling node between the at least two capacitors included in the second capacitor group,
wherein the first power voltage supply terminal and the third power voltage supply terminal are different from each other and receive different power voltages, respectively, and the second power voltage supply terminal and the fourth power voltage supply terminal are different from each other and receive different power voltages, respectively.

2. The reservoir capacitor of claim 1 , wherein each of the first power voltage supply terminal and the third power voltage supply terminal receives one of a power voltage, a high voltage, a core voltage and a bit line precharge voltage and each of the second power voltage supply terminal and the fourth power voltage supply terminal receives a ground voltage or a back bias voltage.

3. The reservoir capacitor of claim 2 , wherein the first power voltage supply terminal and the third power voltage supply terminal receive heterogeneous power voltages.

4. The reservoir capacitor of claim 1 , wherein the capacitor is a stack capacitor having a lower electrode conductive layer, a dielectric substance layer and an upper electrode conductive layer, which are sequentially stacked.

5. The reservoir capacitor of claim 4 , wherein the dielectric substance layer is a thin film having a high-k material or a ferroelectric material.

6. The reservoir capacitor of claim 1 , wherein the first capacitor group comprises:
a first capacitor including a first electrode coupled to the first power voltage supply terminal, a first dielectric substance formed on the first electrode and a second electrode formed on the first dielectric substance; and
a second capacitor including a third electrode coupled to the second power voltage supply terminal, a second dielectric substance formed on the third electrode and a fourth electrode formed on the second dielectric substance.

7. The reservoir capacitor of claim 6 , wherein the first power supply terminal is a first power voltage line for receiving a first power voltage, the first electrode is contacted to the first power voltage line, the second power supply terminal is a second power voltage line for receiving a second power voltage and the third electrode is contacted to the second power voltage line.

8. The reservoir capacitor of claim 7 , wherein the second capacitor group comprises:
a third capacitor including a fifth electrode coupled to the third power voltage supply terminal, a third dielectric substance formed on the fifth electrode and a sixth electrode formed on the third dielectric substance; and
a fourth capacitor including a seventh electrode coupled to the fourth power voltage supply terminal, a fourth dielectric substance formed on the seventh electrode and an eighth electrode formed on the fourth dielectric substance.

9. The reservoir capacitor of claim 8 , wherein the second power voltage supply terminal and the fourth power voltage supply terminal are a common power voltage terminal, the second power voltage line and the fourth power voltage line are a common power voltage line, and the third electrode and the seventh electrode are commonly contacted to the common power voltage line.

10. The reservoir capacitor of claim 8 , wherein the first electrode, the third electrode, the fifth electrode and the seventh electrode are separated by patterning single conductive layer deposited on a substrate.

11. The reservoir capacitor of claim 8 , wherein the second electrode, the fourth electrode, the sixth electrode and the eighth electrode are formed by single conductive layer pattern.

12. The reservoir capacitor of claim 8 , wherein the third power supply terminal is a third power voltage line for receiving a third power voltage, the fifth electrode is contacted to the third power voltage line, the fourth power supply terminal is a fourth power voltage line for receiving a fourth power voltage and the sixth electrode is contacted to the fourth power voltage line.

13. The reservoir capacitor of claim 7 , wherein each of the first power voltage line and the third power voltage line is one selected from a group of a power voltage line, a high voltage line, a core voltage line and a bit line precharge line and each of the second power voltage line and the fourth power voltage line are ground voltage lines or back bias voltage lines.

14. A reservoir capacitor, comprising:
a first capacitor group having at least two capacitor sets, wherein each of the at least two capacitor sets has a plurality of capacitors, which are coupled in parallel, and the at least two capacitor sets are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal;
a second capacitor group having least two capacitor sets, wherein each of the at least two capacitor sets has a plurality of capacitors, which are coupled in parallel, and the at least two capacitor sets are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal; and
a connection line suitable for electrically coupling a first coupling node between the at least two capacitor sets included in the first capacitor group to a second coupling node between the at least two capacitor sets included in the second capacitor group,
wherein the first power voltage supply terminal and the third power voltage supply terminal are different from each other and receive different power voltages, respectively, and the second power voltage supply terminal and the fourth power voltage supply terminal are different from each other and receive different power voltages, respectively.

15. The reservoir capacitor of claim 14 , wherein each of the first power voltage supply terminal and the third power voltage supply terminal receives one of a power voltage, a high voltage, a core voltage and a bit line precharge voltage and each of the second power voltage supply terminal and the fourth power voltage supply terminal receives a ground voltage or a back bias voltage.

16. The reservoir capacitor of claim 15 , wherein the first power voltage supply terminal and the third power voltage supply terminal receive heterogeneous power voltages.

17. The reservoir capacitor of claim 16 , wherein each of the plurality of capacitors is a stack capacitor having a lower electrode conductive layer, a dielectric substance layer and an upper electrode conductive layer, which are sequentially stacked.

18. A semiconductor device, comprising:
a memory cell having a cell capacitor; and
a peripheral circuit having a reservoir capacitor, wherein the reservoir capacitor comprises:
a first capacitor group having at least two capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal;
a second capacitor group having at least two capacitors, which are serially coupled to each other between a third power voltage supply terminal and a

Assignees

• Sk Hynix Inc

Inventors

• Jung Boo-Ho
• Han Sung-Woo
• Oh Ic-Su
• Lee Jun-Ho
• Kim Hyun-Seok
• Cho Sun-Ki
• Kim Tae-Hoon
• Hong Ki-Chul

Classifications

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• H02M11/00 Primary

  Power conversion systems not covered by the preceding groups · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title